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Tue, 13 Feb 2024 18:39:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D325910A10; Tue, 13 Feb 2024 18:38:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bX2JgJNO" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F08C7101EB; Tue, 13 Feb 2024 18:38:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707849533; cv=none; b=DRDWknOfLvW4xmOpbFzMYd44GA4eJemB86nEilNUfOcQiOoikEUpCghbbYEzK+NDXLw1yVwEWy1DvRfBbMt2v29ZqNRI4M1x9YwPwnoY8GTH6jpBTPW7mTwtLL8H53cjPnnQ4bvOM7xlDRrxzD00JCFnQqofbmQXjjojJ9gkEps= ARC-Message-Signature:i=1; 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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="OA9MlAYTsQUv2+OL" Content-Disposition: inline In-Reply-To: <20240213085912.56600-1-prabhakar.mahadev-lad.rj@bp.renesas.com> --OA9MlAYTsQUv2+OL Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 13, 2024 at 08:59:12AM +0000, Prabhakar wrote: > From: Lad Prabhakar >=20 > All the RZ/G2L and alike SoC's (listed below) have ECCRAM0/1 interrupts > supported by the IRQC block, reflect the same in DT binding doc. >=20 > - R9A07G043U - RZ/G2UL > - R9A07G044L/R9A07G044LC - RZ/{G2L,G2LC} > - R9A07G054 - RZ/V2L > - R9A08G045 - RZ/G3S >=20 > For the RZ/G3S SoC ("R9A08G045") ECCRAM0/1 interrupts combined into single > interrupt so we just use the below to represent them: > - ec7tie1-0 > - ec7tie2-0 > - ec7tiovf-0 >=20 > Previously, it was assumed that BUS-error and ECCRAM0/1 error interrupts > were only supported by RZ/G2UL ("R9A07G043U") and RZ/G3S ("R9A08G045") > SoCs. However, in reality, all RZ/G2L and similar SoCs (listed above) > support these interrupts. Therefore, mark the 'interrupt-names' property > as required for all the SoCs and update the example node in the binding > document. >=20 > Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G= 2L Interrupt Controller") > Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-ir= qc: Document RZ/G3S") > Signed-off-by: Lad Prabhakar Acked-by: Conor Dooley Thanks, Conor. --OA9MlAYTsQUv2+OL Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZcu3NwAKCRB4tDGHoIJi 0sqpAP4lmHou9Mu1S56FZF92IyqJH4O/VSL+nY1fJCEbe1kevAD/QhWNEpN20YWw kP/oF4AylBv5Qebw5dN/q5WPRf82Ygw= =m0dc -----END PGP SIGNATURE----- --OA9MlAYTsQUv2+OL--