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Date: Tue, 13 Feb 2024 16:54:44 -0500 (EST)
From: Charles Perry <charles.perry@savoirfairelinux.com>
To: Xu Yilun <yilun.xu@linux.intel.com>, Kris Chaplin <kris.chaplin@amd.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>, mdf <mdf@kernel.org>, 
	Michal Simek <michal.simek@amd.com>, hao wu <hao.wu@intel.com>, 
	yilun xu <yilun.xu@intel.com>, trix <trix@redhat.com>, 
	krzysztof kozlowski+dt <krzysztof.kozlowski+dt@linaro.org>, 
	Brian CODY <bcody@markem-imaje.com>, 
	Allen VANDIVER <avandiver@markem-imaje.com>, 
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Subject: Re: [PATCH 2/3] dt-bindings: fpga: xlnx,fpga-slave-selectmap: add
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On Feb 4, 2024, at 3:30 AM, Xu Yilun yilun.xu@linux.intel.com wrote:
> On Wed, Jan 31, 2024 at 11:03:25AM +0000, Kris Chaplin wrote:
>> Hello Krzysztof,
>> 
>> On 30/01/2024 16:09, Krzysztof Kozlowski wrote:
>> 
>> > > +
>> > > +description: |
>> > > +  Xilinx 7 Series FPGAs support a method of loading the bitstream over a
>> > > +  parallel port named the slave SelectMAP interface in the documentation. Only
>> > > +  the x8 mode is supported where data is loaded at one byte per rising edge of
>> > > +  the clock, with the MSB of each byte presented to the D0 pin.
>> > > +
>> > > +  Datasheets:
>> > > +
>> > > https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
>> > 
>> > I am surprised that AMD/Xilinx still did not update the document to
>> > modern naming (slave->secondary).
>> 
>> Thank you for bringing this up.
>> 
>> We are moving away from using non-inclusive technical terminology and are
>> removing non-inclusive language from our products and related collateral.
>> You will for some time find examples of non-inclusive language, especially
>> in our older products as we work to make these changes and align with
>> industry standards.  For new IP we're ensuring that we switch and stick to
>> inclusive terminology, as you may have seen with my recent w1 driver
>> submission.
>> 
>> SelectMAP is a decades-old interface and as such it is unlikely that we will
>> update this in all documentation dating back this time.  I shall however
>> look to understand what is planned here for active documentation and new
>> driver submissions.
> 
> Yes, I need review from AMD/Xilinx side. Especially the HW parts, and
> some namings of variables, e.g. if xilinx-core is proper for what products
> it supports, and won't be an issue in future.
> 
> Thanks,
> Yilun
> 
>> 
>> regards
>> Kris

Hello,

I chose the "-core" suffix as it seems widely used for core logic of device 
drivers for chips that comes in an i2c and spi flavour. It seems like "-common"
is also widespread, let me know if you prefer that suffix.

As for the HW parts, here's the compatibles used in the v3 patchset for 
convenience:
- xlnx,fpga-xc7s-selectmap
- xlnx,fpga-xc7a-selectmap
- xlnx,fpga-xc7k-selectmap
- xlnx,fpga-xc7v-selectmap

We're trying to be a bit more specific than the spi interface which uses
"xlnx,fpga-slave-serial"

Regards,
Charles