Received-SPF: pass (google.com: domain of linux-kernel+bounces-64605-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1;
Message-ID: <18b3ac3e-2bfc-4fce-9be4-3e75e487f9fc@linux.microsoft.com>
Date: Tue, 13 Feb 2024 16:19:08 -0800
Precedence: bulk
MIME-Version: 1.0
User-Agent: Mozilla Thunderbird
From: Easwar Hariharan <eahariha@linux.microsoft.com>
Subject: Re: [PATCH] arm64: Subscribe Microsoft Azure Cobalt 100 to ARM
 Neoverse N2 errata
To: Oliver Upton <oliver.upton@linux.dev>
Cc: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>,
 Jonathan Corbet <corbet@lwn.net>, Marc Zyngier <maz@kernel.org>,
 Andre Przywara <andre.przywara@arm.com>, Rob Herring <robh@kernel.org>,
 Zenghui Yu <yuzenghui@huawei.com>, Mark Rutland <mark.rutland@arm.com>,
 "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)"
 <linux-arm-kernel@lists.infradead.org>,
 "open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
 open list <linux-kernel@vger.kernel.org>,
 Anshuman Khandual <anshuman.khandual@arm.com>, stable@vger.kernel.org
References: <20240212232909.2276378-1-eahariha@linux.microsoft.com>
 <ZcqtUxhqUbYoRH-G@linux.dev>
Content-Language: en-US
In-Reply-To: <ZcqtUxhqUbYoRH-G@linux.dev>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 7bit

On 2/12/2024 3:44 PM, Oliver Upton wrote:
> Hi Easwar,
> 
> On Mon, Feb 12, 2024 at 11:29:06PM +0000, Easwar Hariharan wrote:
>> Add the MIDR value of Microsoft Azure Cobalt 100, which is a Microsoft
>> implemented CPU based on r0p0 of the ARM Neoverse N2 CPU, and therefore
>> suffers from all the same errata.
> 
> Can you comment at all on where one might find this MIDR? That is, does
> your hypervisor report the native MIDR of the implementation or does it
> repaint it as an Arm Neoverse N2 (0x410FD490)?

We will check on the Microsoft hypervisor's plans, and get back to you.

Notwithstanding that, we do have baremetal use cases for Microsoft Azure Cobalt 100
as well where this MIDR value will show through.

> 
>> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
>> index 7c7493cb571f..a632a7514e55 100644
>> --- a/arch/arm64/include/asm/cputype.h
>> +++ b/arch/arm64/include/asm/cputype.h
>> @@ -61,6 +61,7 @@
>>  #define ARM_CPU_IMP_HISI		0x48
>>  #define ARM_CPU_IMP_APPLE		0x61
>>  #define ARM_CPU_IMP_AMPERE		0xC0
>> +#define ARM_CPU_IMP_MICROSOFT		0x6D
>>  
>>  #define ARM_CPU_PART_AEM_V8		0xD0F
>>  #define ARM_CPU_PART_FOUNDATION		0xD00
>> @@ -135,6 +136,8 @@
>>  
>>  #define AMPERE_CPU_PART_AMPERE1		0xAC3
>>  
>> +#define MSFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */
>> +
>>  #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
>>  #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
>>  #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
>> @@ -193,6 +196,7 @@
>>  #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
>>  #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
>>  #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
>> +#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MSFT_CPU_PART_AZURE_COBALT_100)
> 
> nitpick: consistently use the abbreviated 'MSFT' for all the definitions
> you're adding.
> 

I was rather hoping to use Microsoft throughout, but I chose MSFT for the CPU_PART* to align columns
with the other defines. :) If consistency is of a higher priority than column alignment, I can change it
to MICROSOFT rather than MSFT throughout.

Thanks,
Easwar