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Date: Wed, 14 Feb 2024 12:06:07 +0000
From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Hojin Nam <hj96.nam@samsung.com>
CC: "linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>, Wonjae Lee
	<wj28.lee@samsung.com>, KyungSan Kim <ks0204.kim@samsung.com>,
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	<linux-kernel@vger.kernel.org>, "will@kernel.org" <will@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>
Subject: Re: [PATCH] perf: CXL: fix CPMU filter value mask length
Message-ID: <20240214120607.00002bdd@Huawei.com>
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	<20240214045214epcms2p81d2ea826483fb4aecf19930f2755d55b@epcms2p8>
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On Wed, 14 Feb 2024 13:52:14 +0900
Hojin Nam <hj96.nam@samsung.com> wrote:

> CPMU filter value is described as 4B length in CXL r3.0 8.2.7.2.2.
> However, it is used as 2B length in code and comments.
> 
> Fixes: 5d7107c72796 ("perf: CXL Performance Monitoring Unit driver")
> Signed-off-by: Hojin Nam
Sign off broken.

I have my suspicions about why this is the case (bit of history involved
that I won't go into) but indeed this is wrong. So with SoB fixed.

However, I think the driver only supports HDM filtering currently so
you can't actually hit this. Hence not sure the fixes tag is
appropriate. If you can hit this limitation please post the command.

Worth noting that we still don't have a way to attach this to
switch USPs or host bridges, so the increase in HDM decoders to 32 for
those in r3.1 isn't yet relevant.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
 
> ---
>  drivers/perf/cxl_pmu.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/perf/cxl_pmu.c b/drivers/perf/cxl_pmu.c
> index 365d964b0f6a..ca5e92f28b4a 100644
> --- a/drivers/perf/cxl_pmu.c
> +++ b/drivers/perf/cxl_pmu.c
> @@ -59,7 +59,7 @@
>  #define   CXL_PMU_COUNTER_CFG_EVENT_GRP_ID_IDX_MSK     GENMASK_ULL(63, 59)
> 
>  #define CXL_PMU_FILTER_CFG_REG(n, f)   (0x400 + 4 * ((f) + (n) * 8))
> -#define   CXL_PMU_FILTER_CFG_VALUE_MSK                 GENMASK(15, 0)
> +#define   CXL_PMU_FILTER_CFG_VALUE_MSK                 GENMASK(31, 0)
> 
>  #define CXL_PMU_COUNTER_REG(n)         (0xc00 + 8 * (n))
> 
> @@ -314,9 +314,9 @@ static bool cxl_pmu_config1_get_edge(struct perf_event *event)
>  }
> 
>  /*
> - * CPMU specification allows for 8 filters, each with a 16 bit value...
> - * So we need to find 8x16bits to store it in.
> - * As the value used for disable is 0xffff, a separate enable switch
> + * CPMU specification allows for 8 filters, each with a 32 bit value...
> + * So we need to find 8x32bits to store it in.
> + * As the value used for disable is 0xffff_ffff, a separate enable switch
>   * is needed.
>   */
> 
> @@ -642,7 +642,7 @@ static void cxl_pmu_event_start(struct perf_event *event, int flags)
>                 if (cxl_pmu_config1_hdm_filter_en(event))
>                         cfg = cxl_pmu_config2_get_hdm_decoder(event);
>                 else
> -                       cfg = GENMASK(15, 0); /* No filtering if 0xFFFF_FFFF */
> +                       cfg = GENMASK(31, 0); /* No filtering if 0xFFFF_FFFF */
>                 writeq(cfg, base + CXL_PMU_FILTER_CFG_REG(hwc->idx, 0));
>         }
> 
> --
> 2.34.1