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AJvYcCUaQw52kWuF82VbaukUR2sxp7dkJcD3pWx6eDMo8m3NyyWneAy3W4KOheHKnnMuLq7YRNl+k/hwzZQslW7qnPK7gpDDwE98cvJEkiQRdRKb99ooeMb335uz7twpODLswJxGgiub/BeKbw== X-Gm-Message-State: AOJu0Ywj0YE9BDTLIHURsOHpQjbd0lYPambvJA0P2rzwVtEz2kHnW+ZA COLRO7s9r9GjoYLJ74YTac9F8ZxodGMa2h3JFE8ihr4DFPb0jtSLtwAk+XmCw3+l0GWJUjy6gyl ljbVnSZ7Av10QXYaPqvCl2eqVSz1aUUmsE62Rcg== X-Received: by 2002:a17:90a:5d08:b0:298:a9a5:48ba with SMTP id s8-20020a17090a5d0800b00298a9a548bamr2462478pji.20.1707914147948; Wed, 14 Feb 2024 04:35:47 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240210204606.11944-1-aford173@gmail.com> <20240210204606.11944-3-aford173@gmail.com> <20240214121448.451e2e1c@booty> In-Reply-To: <20240214121448.451e2e1c@booty> From: Adam Ford Date: Wed, 14 Feb 2024 06:35:36 -0600 Message-ID: Subject: Re: [PATCH V4 2/6] phy: freescale: add Samsung HDMI PHY To: Luca Ceresoli Cc: linux-arm-kernel@lists.infradead.org, marex@denx.de, aford@beaconembedded.com, Lucas Stach , Richard Leitner , Marco Felsch , Alexander Stein , Frieder Schrempf , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Catalin Marinas , Will Deacon , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Feb 14, 2024 at 5:14=E2=80=AFAM Luca Ceresoli wrote: > > On Sat, 10 Feb 2024 14:45:58 -0600 > Adam Ford wrote: > > > From: Lucas Stach > > > > This adds the driver for the Samsung HDMI PHY found on the > > i.MX8MP SoC. Based on downstream implementation from > > Sandor Yu . According to the TRM, the PHY > > receives parallel data from the link and serializes it. It > > also sets the PLL clock needed for the TX serializer. > > > > Tested-by: Luca Ceresoli (v2) > > Tested-by: Richard Leitner (v2) > > Co-developed-by: Marco Felsch > > Signed-off-by: Marco Felsch > > Signed-off-by: Lucas Stach > > Tested-by: Alexander Stein > > Tested-by: Frieder Schrempf # Kontron BL > > Tested-by: Luca Ceresoli > > Signed-off-by: Adam Ford > > [...] > > > +static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy) > > +{ > > + struct device *dev =3D phy->dev; > > + struct device_node *np =3D dev->of_node; > > + struct clk_init_data init; > > + const char *parent_name; > > + struct clk *phyclk; > > + int ret; > > + > > + parent_name =3D __clk_get_name(phy->refclk); > > + > > + init.parent_names =3D &parent_name; > > + init.num_parents =3D 1; > > + init.flags =3D 0; > > + init.name =3D "hdmi_pclk"; > > + init.ops =3D &phy_clk_ops; > > + > > + phy->hw.init =3D &init; > > + > > + phyclk =3D devm_clk_register(dev, &phy->hw); > > + if (IS_ERR(phyclk)) > > + return dev_err_probe(dev, PTR_ERR(phyclk), > > + "failed to register clock\n"); > > + > > + ret =3D of_clk_add_provider(np, of_clk_src_simple_get, phyclk); > > As per my v8 review, this function is deprecated: > https://elixir.bootlin.com/linux/v6.8-rc4/source/drivers/clk/clk.c#L4881 > When I found out that the entire driver I pulled was the wrong starting point, and noticed that this version had very little in common with the previous one, I didn't review the feedback knowing tha tI would have thrown away any of the tags from it since it was such a drastic change. I should have caught it, but I missed it, so apologies for that. I will be sure to include this feedback in the next attempt. > However: > > [Tested using Avnet MSC SM2S-IMX8PLUS SoM on Avnet MSC SM2-MB-EP1] > Tested-by: Luca Ceresoli Thanks for testing. adam > > Luca > > -- > Luca Ceresoli, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com