Received-SPF: pass (google.com: domain of linux-kernel+bounces-65333-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99;
Precedence: bulk
MIME-Version: 1.0
References: <20240202-disable_misaligned_probe_config-v3-0-c44f91f03bb6@rivosinc.com>
 <20240202-disable_misaligned_probe_config-v3-2-c44f91f03bb6@rivosinc.com>
In-Reply-To: <20240202-disable_misaligned_probe_config-v3-2-c44f91f03bb6@rivosinc.com>
From: Evan Green <evan@rivosinc.com>
Date: Wed, 14 Feb 2024 09:24:16 -0500
Message-ID: <CALs-HssKav=+P_w5VuoZZU3xkut6FxMUpdpd5HSa5iPMRDu=5A@mail.gmail.com>
Subject: Re: [PATCH v3 2/2] riscv: Disable misaligned access probe when CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
To: Charlie Jenkins <charlie@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Albert Ou <aou@eecs.berkeley.edu>, Jisheng Zhang <jszhang@kernel.org>, 
	=?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= <cleger@rivosinc.com>, 
	Eric Biggers <ebiggers@kernel.org>, Elliot Berman <quic_eberman@quicinc.com>, 
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Fri, Feb 2, 2024 at 6:54=E2=80=AFPM Charlie Jenkins <charlie@rivosinc.co=
m> wrote:
>
> When CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is selected, the cpus can be
> set to have fast misaligned access without needing to probe.
>
> To avoid some ifdefs, move unalignment probing code into its own file
> and make CONFIG_RISCV_MISALIGNED depend on
> CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS.
>
> Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>

One nit below, but feel free to add my tag on the next spin:

Reviewed-by: Evan Green <evan@rivosinc.com>

> ---
>  arch/riscv/Kconfig                          |   1 +
>  arch/riscv/include/asm/cpufeature.h         |   7 +
>  arch/riscv/kernel/Makefile                  |   3 +
>  arch/riscv/kernel/cpufeature.c              | 255 ----------------------=
----
>  arch/riscv/kernel/misaligned_access_speed.c | 265 ++++++++++++++++++++++=
++++++
>  arch/riscv/kernel/sys_hwprobe.c             |   4 +
>  6 files changed, 280 insertions(+), 255 deletions(-)
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index bffbd869a068..3223d2d08f74 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -690,6 +690,7 @@ config THREAD_SIZE_ORDER
>  config RISCV_MISALIGNED
>         bool "Support misaligned load/store traps for kernel and userspac=
e"
>         select SYSCTL_ARCH_UNALIGN_ALLOW
> +       depends on !HAVE_EFFICIENT_UNALIGNED_ACCESS
>         default y
>         help
>           Say Y here if you want the kernel to embed support for misalign=
ed
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm=
/cpufeature.h
> index eb3ac304fc42..44734e5169b1 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -51,6 +51,12 @@ static inline bool check_unaligned_access_emulated(int=
 cpu)
>  static inline void unaligned_emulation_finish(void) {}
>  #endif
>
> +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
> +static __always_inline bool has_fast_misaligned_accesses(void)
> +{
> +       return true;
> +}
> +#else
>  DECLARE_PER_CPU(long, misaligned_access_speed);
>
>  DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
> @@ -59,6 +65,7 @@ static __always_inline bool has_fast_misaligned_accesse=
s(void)
>  {
>         return static_branch_likely(&fast_misaligned_access_speed_key);
>  }
> +#endif
>
>  unsigned long riscv_get_elf_hwcap(void);
>
> diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile
> index f71910718053..ffba5ecf12c2 100644
> --- a/arch/riscv/kernel/Makefile
> +++ b/arch/riscv/kernel/Makefile
> @@ -62,6 +62,9 @@ obj-y +=3D tests/
>  obj-$(CONFIG_MMU) +=3D vdso.o vdso/
>
>  obj-$(CONFIG_RISCV_MISALIGNED) +=3D traps_misaligned.o
> +ifneq ($(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS), y)
> +obj-y  +=3D misaligned_access_speed.o

copy-unaligned.o can also go in here (those are the assembly copy
routines used only by the probing code).

> +endif
>  obj-$(CONFIG_FPU)              +=3D fpu.o
>  obj-$(CONFIG_RISCV_ISA_V)      +=3D vector.o
>  obj-$(CONFIG_RISCV_ISA_V)      +=3D kernel_mode_vector.o
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeatur=
e.c
> index 89920f84d0a3..319670af5704 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -11,7 +11,6 @@
>  #include <linux/cpu.h>
>  #include <linux/cpuhotplug.h>
>  #include <linux/ctype.h>
> -#include <linux/jump_label.h>
>  #include <linux/log2.h>
>  #include <linux/memory.h>
>  #include <linux/module.h>
> @@ -21,20 +20,12 @@
>  #include <asm/cacheflush.h>
>  #include <asm/cpufeature.h>
>  #include <asm/hwcap.h>
> -#include <asm/hwprobe.h>
>  #include <asm/patch.h>
>  #include <asm/processor.h>
>  #include <asm/vector.h>
>
> -#include "copy-unaligned.h"
> -
>  #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
>
> -#define MISALIGNED_ACCESS_JIFFIES_LG2 1
> -#define MISALIGNED_BUFFER_SIZE 0x4000
> -#define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE)
> -#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
> -
>  unsigned long elf_hwcap __read_mostly;
>
>  /* Host ISA bitmap */
> @@ -43,11 +34,6 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __=
read_mostly;
>  /* Per-cpu ISA extensions. */
>  struct riscv_isainfo hart_isa[NR_CPUS];
>
> -/* Performance information */
> -DEFINE_PER_CPU(long, misaligned_access_speed);
> -
> -static cpumask_t fast_misaligned_access;
> -
>  /**
>   * riscv_isa_extension_base() - Get base extension word
>   *
> @@ -706,247 +692,6 @@ unsigned long riscv_get_elf_hwcap(void)
>         return hwcap;
>  }
>
> -static int check_unaligned_access(void *param)
> -{
> -       int cpu =3D smp_processor_id();
> -       u64 start_cycles, end_cycles;
> -       u64 word_cycles;
> -       u64 byte_cycles;
> -       int ratio;
> -       unsigned long start_jiffies, now;
> -       struct page *page =3D param;
> -       void *dst;
> -       void *src;
> -       long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW;
> -
> -       if (check_unaligned_access_emulated(cpu))
> -               return 0;
> -
> -       /* Make an unaligned destination buffer. */
> -       dst =3D (void *)((unsigned long)page_address(page) | 0x1);
> -       /* Unalign src as well, but differently (off by 1 + 2 =3D 3). */
> -       src =3D dst + (MISALIGNED_BUFFER_SIZE / 2);
> -       src +=3D 2;
> -       word_cycles =3D -1ULL;
> -       /* Do a warmup. */
> -       __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE);
> -       preempt_disable();
> -       start_jiffies =3D jiffies;
> -       while ((now =3D jiffies) =3D=3D start_jiffies)
> -               cpu_relax();
> -
> -       /*
> -        * For a fixed amount of time, repeatedly try the function, and t=
ake
> -        * the best time in cycles as the measurement.
> -        */
> -       while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES=
_LG2))) {
> -               start_cycles =3D get_cycles64();
> -               /* Ensure the CSR read can't reorder WRT to the copy. */
> -               mb();
> -               __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SI=
ZE);
> -               /* Ensure the copy ends before the end time is snapped. *=
/
> -               mb();
> -               end_cycles =3D get_cycles64();
> -               if ((end_cycles - start_cycles) < word_cycles)
> -                       word_cycles =3D end_cycles - start_cycles;
> -       }
> -
> -       byte_cycles =3D -1ULL;
> -       __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE);
> -       start_jiffies =3D jiffies;
> -       while ((now =3D jiffies) =3D=3D start_jiffies)
> -               cpu_relax();
> -
> -       while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES=
_LG2))) {
> -               start_cycles =3D get_cycles64();
> -               mb();
> -               __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SI=
ZE);
> -               mb();
> -               end_cycles =3D get_cycles64();
> -               if ((end_cycles - start_cycles) < byte_cycles)
> -                       byte_cycles =3D end_cycles - start_cycles;
> -       }
> -
> -       preempt_enable();
> -
> -       /* Don't divide by zero. */
> -       if (!word_cycles || !byte_cycles) {
> -               pr_warn("cpu%d: rdtime lacks granularity needed to measur=
e unaligned access speed\n",
> -                       cpu);
> -
> -               return 0;
> -       }
> -
> -       if (word_cycles < byte_cycles)
> -               speed =3D RISCV_HWPROBE_MISALIGNED_FAST;
> -
> -       ratio =3D div_u64((byte_cycles * 100), word_cycles);
> -       pr_info("cpu%d: Ratio of byte access time to unaligned word acces=
s is %d.%02d, unaligned accesses are %s\n",
> -               cpu,
> -               ratio / 100,
> -               ratio % 100,
> -               (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "=
slow");
> -
> -       per_cpu(misaligned_access_speed, cpu) =3D speed;
> -
> -       /*
> -        * Set the value of fast_misaligned_access of a CPU. These operat=
ions
> -        * are atomic to avoid race conditions.
> -        */
> -       if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST)
> -               cpumask_set_cpu(cpu, &fast_misaligned_access);
> -       else
> -               cpumask_clear_cpu(cpu, &fast_misaligned_access);
> -
> -       return 0;
> -}
> -
> -static void check_unaligned_access_nonboot_cpu(void *param)
> -{
> -       unsigned int cpu =3D smp_processor_id();
> -       struct page **pages =3D param;
> -
> -       if (smp_processor_id() !=3D 0)
> -               check_unaligned_access(pages[cpu]);
> -}
> -
> -DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
> -
> -static void modify_unaligned_access_branches(cpumask_t *mask, int weight=
)
> -{
> -       if (cpumask_weight(mask) =3D=3D weight)
> -               static_branch_enable_cpuslocked(&fast_misaligned_access_s=
peed_key);
> -       else
> -               static_branch_disable_cpuslocked(&fast_misaligned_access_=
speed_key);
> -}
> -
> -static void set_unaligned_access_static_branches_except_cpu(int cpu)
> -{
> -       /*
> -        * Same as set_unaligned_access_static_branches, except excludes =
the
> -        * given CPU from the result. When a CPU is hotplugged into an of=
fline
> -        * state, this function is called before the CPU is set to offlin=
e in
> -        * the cpumask, and thus the CPU needs to be explicitly excluded.
> -        */
> -
> -       cpumask_t fast_except_me;
> -
> -       cpumask_and(&fast_except_me, &fast_misaligned_access, cpu_online_=
mask);
> -       cpumask_clear_cpu(cpu, &fast_except_me);
> -
> -       modify_unaligned_access_branches(&fast_except_me, num_online_cpus=
() - 1);
> -}
> -
> -static void set_unaligned_access_static_branches(void)
> -{
> -       /*
> -        * This will be called after check_unaligned_access_all_cpus so t=
he
> -        * result of unaligned access speed for all CPUs will be availabl=
e.
> -        *
> -        * To avoid the number of online cpus changing between reading
> -        * cpu_online_mask and calling num_online_cpus, cpus_read_lock mu=
st be
> -        * held before calling this function.
> -        */
> -
> -       cpumask_t fast_and_online;
> -
> -       cpumask_and(&fast_and_online, &fast_misaligned_access, cpu_online=
_mask);
> -
> -       modify_unaligned_access_branches(&fast_and_online, num_online_cpu=
s());
> -}
> -
> -static int lock_and_set_unaligned_access_static_branch(void)
> -{
> -       cpus_read_lock();
> -       set_unaligned_access_static_branches();
> -       cpus_read_unlock();
> -
> -       return 0;
> -}
> -
> -arch_initcall_sync(lock_and_set_unaligned_access_static_branch);
> -
> -static int riscv_online_cpu(unsigned int cpu)
> -{
> -       static struct page *buf;
> -
> -       /* We are already set since the last check */
> -       if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISA=
LIGNED_UNKNOWN)
> -               goto exit;
> -
> -       buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);
> -       if (!buf) {
> -               pr_warn("Allocation failure, not measuring misaligned per=
formance\n");
> -               return -ENOMEM;
> -       }
> -
> -       check_unaligned_access(buf);
> -       __free_pages(buf, MISALIGNED_BUFFER_ORDER);
> -
> -exit:
> -       set_unaligned_access_static_branches();
> -
> -       return 0;
> -}
> -
> -static int riscv_offline_cpu(unsigned int cpu)
> -{
> -       set_unaligned_access_static_branches_except_cpu(cpu);
> -
> -       return 0;
> -}
> -
> -/* Measure unaligned access on all CPUs present at boot in parallel. */
> -static int check_unaligned_access_all_cpus(void)
> -{
> -       unsigned int cpu;
> -       unsigned int cpu_count =3D num_possible_cpus();
> -       struct page **bufs =3D kzalloc(cpu_count * sizeof(struct page *),
> -                                    GFP_KERNEL);
> -
> -       if (!bufs) {
> -               pr_warn("Allocation failure, not measuring misaligned per=
formance\n");
> -               return 0;
> -       }
> -
> -       /*
> -        * Allocate separate buffers for each CPU so there's no fighting =
over
> -        * cache lines.
> -        */
> -       for_each_cpu(cpu, cpu_online_mask) {
> -               bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_O=
RDER);
> -               if (!bufs[cpu]) {
> -                       pr_warn("Allocation failure, not measuring misali=
gned performance\n");
> -                       goto out;
> -               }
> -       }
> -
> -       /* Check everybody except 0, who stays behind to tend jiffies. */
> -       on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1);
> -
> -       /* Check core 0. */
> -       smp_call_on_cpu(0, check_unaligned_access, bufs[0], true);
> -
> -       /*
> -        * Setup hotplug callbacks for any new CPUs that come online or g=
o
> -        * offline.
> -        */
> -       cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online",
> -                                 riscv_online_cpu, riscv_offline_cpu);
> -
> -out:
> -       unaligned_emulation_finish();
> -       for_each_cpu(cpu, cpu_online_mask) {
> -               if (bufs[cpu])
> -                       __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER);
> -       }
> -
> -       kfree(bufs);
> -       return 0;
> -}
> -
> -arch_initcall(check_unaligned_access_all_cpus);
> -
>  void riscv_user_isa_enable(void)
>  {
>         if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_IS=
A_EXT_ZICBOZ))
> diff --git a/arch/riscv/kernel/misaligned_access_speed.c b/arch/riscv/ker=
nel/misaligned_access_speed.c
> new file mode 100644
> index 000000000000..b725c07dd1af
> --- /dev/null
> +++ b/arch/riscv/kernel/misaligned_access_speed.c
> @@ -0,0 +1,265 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2024 Rivos Inc.
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/cpumask.h>
> +#include <linux/jump_label.h>
> +#include <linux/mm.h>
> +#include <linux/smp.h>
> +#include <linux/types.h>
> +#include <asm/cpufeature.h>
> +#include <asm/hwprobe.h>
> +
> +#include "copy-unaligned.h"
> +
> +#define MISALIGNED_ACCESS_JIFFIES_LG2 1
> +#define MISALIGNED_BUFFER_SIZE 0x4000
> +#define MISALIGNED_BUFFER_ORDER get_order(MISALIGNED_BUFFER_SIZE)
> +#define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
> +
> +DEFINE_PER_CPU(long, misaligned_access_speed);
> +
> +static cpumask_t fast_misaligned_access;
> +
> +static int check_unaligned_access(void *param)
> +{
> +       int cpu =3D smp_processor_id();
> +       u64 start_cycles, end_cycles;
> +       u64 word_cycles;
> +       u64 byte_cycles;
> +       int ratio;
> +       unsigned long start_jiffies, now;
> +       struct page *page =3D param;
> +       void *dst;
> +       void *src;
> +       long speed =3D RISCV_HWPROBE_MISALIGNED_SLOW;
> +
> +       if (check_unaligned_access_emulated(cpu))
> +               return 0;
> +
> +       /* Make an unaligned destination buffer. */
> +       dst =3D (void *)((unsigned long)page_address(page) | 0x1);
> +       /* Unalign src as well, but differently (off by 1 + 2 =3D 3). */
> +       src =3D dst + (MISALIGNED_BUFFER_SIZE / 2);
> +       src +=3D 2;
> +       word_cycles =3D -1ULL;
> +       /* Do a warmup. */
> +       __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SIZE);
> +       preempt_disable();
> +       start_jiffies =3D jiffies;
> +       while ((now =3D jiffies) =3D=3D start_jiffies)
> +               cpu_relax();
> +
> +       /*
> +        * For a fixed amount of time, repeatedly try the function, and t=
ake
> +        * the best time in cycles as the measurement.
> +        */
> +       while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES=
_LG2))) {
> +               start_cycles =3D get_cycles64();
> +               /* Ensure the CSR read can't reorder WRT to the copy. */
> +               mb();
> +               __riscv_copy_words_unaligned(dst, src, MISALIGNED_COPY_SI=
ZE);
> +               /* Ensure the copy ends before the end time is snapped. *=
/
> +               mb();
> +               end_cycles =3D get_cycles64();
> +               if ((end_cycles - start_cycles) < word_cycles)
> +                       word_cycles =3D end_cycles - start_cycles;
> +       }
> +
> +       byte_cycles =3D -1ULL;
> +       __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SIZE);
> +       start_jiffies =3D jiffies;
> +       while ((now =3D jiffies) =3D=3D start_jiffies)
> +               cpu_relax();
> +
> +       while (time_before(jiffies, now + (1 << MISALIGNED_ACCESS_JIFFIES=
_LG2))) {
> +               start_cycles =3D get_cycles64();
> +               mb();
> +               __riscv_copy_bytes_unaligned(dst, src, MISALIGNED_COPY_SI=
ZE);
> +               mb();
> +               end_cycles =3D get_cycles64();
> +               if ((end_cycles - start_cycles) < byte_cycles)
> +                       byte_cycles =3D end_cycles - start_cycles;
> +       }
> +
> +       preempt_enable();
> +
> +       /* Don't divide by zero. */
> +       if (!word_cycles || !byte_cycles) {
> +               pr_warn("cpu%d: rdtime lacks granularity needed to measur=
e unaligned access speed\n",
> +                       cpu);
> +
> +               return 0;
> +       }
> +
> +       if (word_cycles < byte_cycles)
> +               speed =3D RISCV_HWPROBE_MISALIGNED_FAST;
> +
> +       ratio =3D div_u64((byte_cycles * 100), word_cycles);
> +       pr_info("cpu%d: Ratio of byte access time to unaligned word acces=
s is %d.%02d, unaligned accesses are %s\n",
> +               cpu,
> +               ratio / 100,
> +               ratio % 100,
> +               (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST) ? "fast" : "=
slow");
> +
> +       per_cpu(misaligned_access_speed, cpu) =3D speed;
> +
> +       /*
> +        * Set the value of fast_misaligned_access of a CPU. These operat=
ions
> +        * are atomic to avoid race conditions.
> +        */
> +       if (speed =3D=3D RISCV_HWPROBE_MISALIGNED_FAST)
> +               cpumask_set_cpu(cpu, &fast_misaligned_access);
> +       else
> +               cpumask_clear_cpu(cpu, &fast_misaligned_access);
> +
> +       return 0;
> +}
> +
> +static void check_unaligned_access_nonboot_cpu(void *param)
> +{
> +       unsigned int cpu =3D smp_processor_id();
> +       struct page **pages =3D param;
> +
> +       if (smp_processor_id() !=3D 0)
> +               check_unaligned_access(pages[cpu]);
> +}
> +
> +DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key);
> +
> +static void modify_unaligned_access_branches(cpumask_t *mask, int weight=
)
> +{
> +       if (cpumask_weight(mask) =3D=3D weight)
> +               static_branch_enable_cpuslocked(&fast_misaligned_access_s=
peed_key);
> +       else
> +               static_branch_disable_cpuslocked(&fast_misaligned_access_=
speed_key);
> +}
> +
> +static void set_unaligned_access_static_branches_except_cpu(int cpu)
> +{
> +       /*
> +        * Same as set_unaligned_access_static_branches, except excludes =
the
> +        * given CPU from the result. When a CPU is hotplugged into an of=
fline
> +        * state, this function is called before the CPU is set to offlin=
e in
> +        * the cpumask, and thus the CPU needs to be explicitly excluded.
> +        */
> +
> +       cpumask_t fast_except_me;
> +
> +       cpumask_and(&fast_except_me, &fast_misaligned_access, cpu_online_=
mask);
> +       cpumask_clear_cpu(cpu, &fast_except_me);
> +
> +       modify_unaligned_access_branches(&fast_except_me, num_online_cpus=
() - 1);
> +}
> +
> +static void set_unaligned_access_static_branches(void)
> +{
> +       /*
> +        * This will be called after check_unaligned_access_all_cpus so t=
he
> +        * result of unaligned access speed for all CPUs will be availabl=
e.
> +        *
> +        * To avoid the number of online cpus changing between reading
> +        * cpu_online_mask and calling num_online_cpus, cpus_read_lock mu=
st be
> +        * held before calling this function.
> +        */
> +
> +       cpumask_t fast_and_online;
> +
> +       cpumask_and(&fast_and_online, &fast_misaligned_access, cpu_online=
_mask);
> +
> +       modify_unaligned_access_branches(&fast_and_online, num_online_cpu=
s());
> +}
> +
> +static int lock_and_set_unaligned_access_static_branch(void)
> +{
> +       cpus_read_lock();
> +       set_unaligned_access_static_branches();
> +       cpus_read_unlock();
> +
> +       return 0;
> +}
> +
> +arch_initcall_sync(lock_and_set_unaligned_access_static_branch);
> +
> +static int riscv_online_cpu(unsigned int cpu)
> +{
> +       static struct page *buf;
> +
> +       /* We are already set since the last check */
> +       if (per_cpu(misaligned_access_speed, cpu) !=3D RISCV_HWPROBE_MISA=
LIGNED_UNKNOWN)
> +               goto exit;
> +
> +       buf =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER);
> +       if (!buf) {
> +               pr_warn("Allocation failure, not measuring misaligned per=
formance\n");
> +               return -ENOMEM;
> +       }
> +
> +       check_unaligned_access(buf);
> +       __free_pages(buf, MISALIGNED_BUFFER_ORDER);
> +
> +exit:
> +       set_unaligned_access_static_branches();
> +
> +       return 0;
> +}
> +
> +static int riscv_offline_cpu(unsigned int cpu)
> +{
> +       set_unaligned_access_static_branches_except_cpu(cpu);
> +
> +       return 0;
> +}
> +
> +/* Measure unaligned access on all CPUs present at boot in parallel. */
> +static int check_unaligned_access_all_cpus(void)
> +{
> +       unsigned int cpu;
> +       unsigned int cpu_count =3D num_possible_cpus();
> +       struct page **bufs =3D kzalloc(cpu_count * sizeof(struct page *),
> +                                    GFP_KERNEL);
> +
> +       if (!bufs) {
> +               pr_warn("Allocation failure, not measuring misaligned per=
formance\n");
> +               return 0;
> +       }
> +
> +       /*
> +        * Allocate separate buffers for each CPU so there's no fighting =
over
> +        * cache lines.
> +        */
> +       for_each_cpu(cpu, cpu_online_mask) {
> +               bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_O=
RDER);
> +               if (!bufs[cpu]) {
> +                       pr_warn("Allocation failure, not measuring misali=
gned performance\n");
> +                       goto out;
> +               }
> +       }
> +
> +       /* Check everybody except 0, who stays behind to tend jiffies. */
> +       on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1);
> +
> +       /* Check core 0. */
> +       smp_call_on_cpu(0, check_unaligned_access, bufs[0], true);
> +
> +       /*
> +        * Setup hotplug callbacks for any new CPUs that come online or g=
o
> +        * offline.
> +        */
> +       cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online",
> +                                 riscv_online_cpu, riscv_offline_cpu);
> +
> +out:
> +       unaligned_emulation_finish();
> +       for_each_cpu(cpu, cpu_online_mask) {
> +               if (bufs[cpu])
> +                       __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER);
> +       }
> +
> +       kfree(bufs);
> +       return 0;
> +}
> +
> +arch_initcall(check_unaligned_access_all_cpus);
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwpr=
obe.c
> index a7c56b41efd2..d9bd24776a3e 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -149,6 +149,9 @@ static bool hwprobe_ext0_has(const struct cpumask *cp=
us, unsigned long ext)
>
>  static u64 hwprobe_misaligned(const struct cpumask *cpus)
>  {
> +#ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
> +       return RISCV_HWPROBE_MISALIGNED_FAST;
> +#else

Ok, two nits, this is a little clunky with the ifdef inside the
function body. The pattern I see more often is the ifdef/else each
containing a separate function definition. That would work nicely
here.

>         int cpu;
>         u64 perf =3D -1ULL;
>
> @@ -168,6 +171,7 @@ static u64 hwprobe_misaligned(const struct cpumask *c=
pus)
>                 return RISCV_HWPROBE_MISALIGNED_UNKNOWN;
>
>         return perf;
> +#endif
>  }
>
>  static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>
> --
> 2.43.0
>