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Wysocki" , Andrew Davis , , , , Subject: Re: [PATCH 1/3] dt-bindings: cpufreq: Add nvmem-cells for chip information Message-ID: <20240215085951.xrcitu2so5gqcewn@dhruva> References: <20240206145721.2418893-1-msp@baylibre.com> <20240206145721.2418893-2-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240206145721.2418893-2-msp@baylibre.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Hi, On Feb 06, 2024 at 15:57:19 +0100, Markus Schneider-Pargmann wrote: > Add nvmem-cells to describe chip information like chipvariant and > chipspeed. If nvmem-cells are used, the syscon property is not necessary > anymore. > > Signed-off-by: Markus Schneider-Pargmann > Acked-by: Andrew Davis > --- > .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > index 02d1d2c17129..b1881a0834fe 100644 > --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml > @@ -34,6 +34,14 @@ properties: > points to syscon node representing the control module > register space of the SoC. > > + nvmem-cells: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + > + nvmem-cell-names: > + items: > + - const: chipvariant > + - const: chipspeed > + > opp-shared: true > > patternProperties: > @@ -55,7 +63,13 @@ patternProperties: > > required: > - compatible > - - syscon > + > +oneOf: > + - required: > + - syscon > + - required: > + - nvmem-cells > + - nvmem-cell-names Reviewed-by: Dhruva Gole -- Best regards, Dhruva Gole