Received: by 2002:a05:7412:1e0b:b0:fc:a2b0:25d7 with SMTP id kr11csp358375rdb; Thu, 15 Feb 2024 02:16:09 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUvGIz3Of3LOxryVN9xYLwgZppnsXIzLiQzCInKEWXAB+J03m7odP5mlOWYr5tTwD9s6N9PeQXkgtsxepn1ujYSbaBgjzI8RN4KkOzVHA== X-Google-Smtp-Source: AGHT+IFzlp61PTbyFwgF4//bz/VG1ZZ/y2Alfj+QGlNdhAsC/Kybg+EBXPLVEnbf98kaafEQIrjs X-Received: by 2002:a17:902:eccb:b0:1db:8fd6:bf87 with SMTP id a11-20020a170902eccb00b001db8fd6bf87mr573261plh.32.1707992169119; Thu, 15 Feb 2024 02:16:09 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707992169; cv=pass; d=google.com; s=arc-20160816; b=MTD8/Stmce5d2IYtzRxyfktmAYafy6WnEHYa6gRo2a4ByUBrerMpwJbjVdD0TCneqo l1c3nrOdr9efzDEEw9X7ZFFznsz0NDvbZLejJiO5N57CqHCI0/PMJ9knN0lGOsFjDCI5 pfa1C60IunyzpaDVlMoZojOgljAycIb6hT2Yzceh1MQiuDElW7P8KWqihBBTAMBnaiLY Tc9SQm05ssoY+kCgniOKBUXHAnraklA6REnjKL0X4IkVvNW8m2BU/W8dTX/+Mlnf3M45 eSzhLTH7R5J+Cmz897qaoraepdkx+4RX0hTEtv+7oMWYNRjHN0F2kC5IDwsJ4KtZNp5R CwUg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=mime-version:list-unsubscribe:list-subscribe:list-id:precedence :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y5O9N7gBJ9YynX66Tx+xiBM4fZt9lzNxS+JsnlX7gZc=; fh=PWpMUFySz/+abNBcZMGAF+1x8Vi76p56GtPU1dgQSG4=; b=IQjYk8og6iUI0mvh0ySkjoOD1d/z95gu2/dmHylcjXyLXfy05LMeC4FxFsagh5NwpK VWJisUztXDK+a3gJrnp7kvgCfWqtWbhP7/gzN6MhIhx0vFHIxXg5H0xvHUWfu6XCwZyi R16QzOCbjdGTgBw2aGz2P0Kvg4F7MnCV2Cdl+gmserde7MX6MTxmPdX3Y2pzfW0lQqnh s80zTFlDNtcxkfjtlptN9lwAeOdBagv9lh8FOnQJ1PY1yowK/0MmGt3q+Cf4Mm5dppvE mWgV+m7b/l2ULBNt8wvuNzABHF0/CmLKsFEuf9dJSfK5eLtiOO9wsHWf8rti7X6CuzBM 3chA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="Jg9Ts9v/"; arc=pass (i=1 spf=pass spfdomain=mediatek.com dkim=pass dkdomain=mediatek.com dmarc=pass fromdomain=mediatek.com); spf=pass (google.com: domain of linux-kernel+bounces-66609-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66609-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id j12-20020a170903024c00b001d5e9f77cf3si926528plh.79.2024.02.15.02.16.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 02:16:09 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-66609-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="Jg9Ts9v/"; arc=pass (i=1 spf=pass spfdomain=mediatek.com dkim=pass dkdomain=mediatek.com dmarc=pass fromdomain=mediatek.com); spf=pass (google.com: domain of linux-kernel+bounces-66609-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-66609-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 1FC8C283D38 for ; Thu, 15 Feb 2024 10:14:47 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6C897745F1; Thu, 15 Feb 2024 10:11:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Jg9Ts9v/" Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D73806A356 for ; Thu, 15 Feb 2024 10:11:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; cv=none; b=mwobVs/RY4sOmMJdN97gBXudyAwUIPGlkvZUDIR8r6zg1MmUmbPybcKxieYMm1A9zRAvPNh1QIl9fjHRgi4E2iFsy+wIgpaccAWy/oG0uPZOxh2Qn8knoKD/6pDVvx3UezBmKtsXNQFDh0TM9BKvJl2kjzg0NHRBXhWaSq4DFqU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707991895; c=relaxed/simple; bh=oVScb3QsrAhkut/wVNKk0Gm6+3u3IV95GPV0PD1mYSA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XinpvftT/XnjADRdZ9Qszw/DnD+2yWQqrPqfRzJtWBsPwLo8cnQvUcCygtnYt+WTjF6e9R7H7nHIZn9cFD7s1pNo43Izq+uUmya//G4JLC7OBXuuVHT/B1jMVKklANBymu7iRScoY3Gml0Ca7NR9RzgRzbeVR5PRakFJ0SmLf+s= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=Jg9Ts9v/; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com X-UUID: 925cf3a8cbea11eea2298b7352fd921d-20240215 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=y5O9N7gBJ9YynX66Tx+xiBM4fZt9lzNxS+JsnlX7gZc=; b=Jg9Ts9v/wAJn20EFSLEfBEenp/cveHgQ9xbxlAZM4IM2yVkeghDe2jThdigU2k2RtjT1ZWiI38LJ/sCymwfzjAfDlm6YT7z7t89Wl3z8rXKNOZiqEAGKiGv5O5fL0qmF3o+4LSBE9qZzHuL8pD27vnf+K/PCQ9yOxy/b19fgXWU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:a889ad8b-d6df-43b2-a105-d374a6b9e3e8,IP:0,U RL:0,TC:0,Content:-25,EDM:-25,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACT ION:release,TS:-50 X-CID-META: VersionHash:6f543d0,CLOUDID:0d70eb83-8d4f-477b-89d2-1e3bdbef96d1,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:1,IP:nil,UR L:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,S PR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 925cf3a8cbea11eea2298b7352fd921d-20240215 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 533599165; Thu, 15 Feb 2024 18:11:23 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 15 Feb 2024 18:11:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 15 Feb 2024 18:11:21 +0800 From: Hsiao Chien Sung To: AngeloGioacchino Del Regno , Chun-Kuang Hu CC: Philipp Zabel , David Airlie , Daniel Vetter , Matthias Brugger , Bibby Hsieh , CK Hu , Sean Paul , Fei Shao , Jason Chen , "Nancy . Lin" , , , , , Hsiao Chien Sung Subject: [PATCH v5 04/13] drm/mediatek: Fix errors when reporting rotation capability Date: Thu, 15 Feb 2024 18:11:10 +0800 Message-ID: <20240215101119.12629-5-shawn.sung@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20240215101119.12629-1-shawn.sung@mediatek.com> References: <20240215101119.12629-1-shawn.sung@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--5.636000-8.000000 X-TMASE-MatchedRID: qKC9Lion//KU2fVedEQUO2NW0DAjL5p+Wot5Z16+u77vnm3ZesFzgvKC 81FnsF5IlTJXKqh1ne2rjfxn0AirrC2W7Y+Npd9Rh2VzUlo4HVNPZ8WbDkfxU56fSoF3Lt+M6bg Zy139hG9UOKk2VxzSJ1ixvQr0+Z/MOnfMHqHi4mn0mf9msa5zwdspPGnf5a0gmyiLZetSf8mfop 0ytGwvXiq2rl3dzGQ1vgPmisnFUWbXwI/jONLDvC7HnNEcltGLYnt8a3k1TsX/KqpkYjIexsC+k sT6a9fy X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.636000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: E90F10E76A8687E0E18E0F690897B51CE0CC013172CA94CC015DE292832A8D4D2000:8 X-MTK: N Create rotation property according to the hardware capability. Since currently OVL of all chips support same rotation, no need to define it in the driver data. Fixes: 84d805753983 ("drm/mediatek: Support reflect-y plane rotation") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Hsiao Chien Sung --- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 + drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 19 +++++++------------ .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 9 +++++++++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + drivers/gpu/drm/mediatek/mtk_drm_plane.c | 2 +- 5 files changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 4a5661334fb1a..cd5ca5359b0f0 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -126,6 +126,7 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(vo void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev); void mtk_ovl_adaptor_enable_vblank(struct device *dev); void mtk_ovl_adaptor_disable_vblank(struct device *dev); +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev); void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c index 5aaf4342cdbda..c42fce38a35eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -289,6 +289,10 @@ unsigned int mtk_ovl_layer_nr(struct device *dev) unsigned int mtk_ovl_supported_rotations(struct device *dev) { + /* + * although currently OVL can only do reflection, + * reflect x + reflect y = rotate 180 + */ return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y; } @@ -297,27 +301,18 @@ int mtk_ovl_layer_check(struct device *dev, unsigned int idx, struct mtk_plane_state *mtk_state) { struct drm_plane_state *state = &mtk_state->base; - unsigned int rotation = 0; - rotation = drm_rotation_simplify(state->rotation, - DRM_MODE_ROTATE_0 | - DRM_MODE_REFLECT_X | - DRM_MODE_REFLECT_Y); - rotation &= ~DRM_MODE_ROTATE_0; - - /* We can only do reflection, not rotation */ - if ((rotation & DRM_MODE_ROTATE_MASK) != 0) + /* check if any unsupported rotation is set */ + if (state->rotation & ~mtk_ovl_supported_rotations(dev)) return -EINVAL; /* * TODO: Rotating/reflecting YUV buffers is not supported at this time. * Only RGB[AX] variants are supported. */ - if (state->fb->format->is_yuv && rotation != 0) + if (state->fb->format->is_yuv && (state->rotation & ~DRM_MODE_ROTATE_0)) return -EINVAL; - state->rotation = rotation; - return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c index 6d4334955e3d3..d4a13a1402148 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -379,6 +379,15 @@ void mtk_ovl_adaptor_register_vblank_cb(struct device *dev, void (*vblank_cb)(vo vblank_cb, vblank_cb_data); } +unsigned int mtk_ovl_adaptor_supported_rotations(struct device *dev) +{ + /* + * should still return DRM_MODE_ROTATE_0 if rotation is not supported, + * or IGT will fail. + */ + return DRM_MODE_ROTATE_0; +} + void mtk_ovl_adaptor_unregister_vblank_cb(struct device *dev) { struct mtk_disp_ovl_adaptor *ovl_adaptor = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 94590227c56a9..b47be6955d9b8 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -417,6 +417,7 @@ static const struct mtk_ddp_comp_funcs ddp_ovl_adaptor = { .get_formats = mtk_ovl_adaptor_get_formats, .get_num_formats = mtk_ovl_adaptor_get_num_formats, .mode_valid = mtk_ovl_adaptor_mode_valid, + .supported_rotations = mtk_ovl_adaptor_supported_rotations, }; static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c index f10d4cc6c2234..2dc28a79f7603 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c @@ -338,7 +338,7 @@ int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane, return err; } - if (supported_rotations & ~DRM_MODE_ROTATE_0) { + if (supported_rotations) { err = drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, supported_rotations); -- 2.18.0