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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL02EPF0001A0FB.mail.protection.outlook.com (10.167.242.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Thu, 15 Feb 2024 11:31:58 +0000 Received: from gomati.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 05:31:54 -0600 From: Nikunj A Dadhania To: , , , , CC: , , , , , , Subject: [PATCH v8 00/16] Add Secure TSC support for SNP guests Date: Thu, 15 Feb 2024 17:01:12 +0530 Message-ID: <20240215113128.275608-1-nikunj@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FB:EE_|CH0PR12MB5124:EE_ X-MS-Office365-Filtering-Correlation-Id: 3517c517-43fc-4709-f53e-08dc2e19b859 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 11:31:58.1262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3517c517-43fc-4709-f53e-08dc2e19b859 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5124 This patchset is also available at: https://github.com/AMDESE/linux-kvm/tree/sectsc-guest-latest and is based on tip/x86/sev base commit ee8ff8768735 ("crypto: ccp - Have it depend on AMD_IOMMU") Overview -------- Secure TSC allows guests to securely use RDTSC/RDTSCP instructions as the parameters being used cannot be changed by hypervisor once the guest is launched. More details in the AMD64 APM Vol 2, Section "Secure TSC". During the boot-up of the secondary cpus, SecureTSC enabled guests need to query TSC info from AMD Security Processor. This communication channel is encrypted between the AMD Security Processor and the guest, the hypervisor is just the conduit to deliver the guest messages to the AMD Security Processor. Each message is protected with an AEAD (AES-256 GCM). See "SEV Secure Nested Paging Firmware ABI Specification" document (currently at https://www.amd.com/system/files/TechDocs/56860.pdf) section "TSC Info" Use a minimal GCM library to encrypt/decrypt SNP Guest messages to communicate with the AMD Security Processor which is available at early boot. SEV-guest driver has the implementation for guest and AMD Security Processor communication. As the TSC_INFO needs to be initialized during early boot before smp cpus are started, move most of the sev-guest driver code to kernel/sev.c and provide well defined APIs to the sev-guest driver to use the interface to avoid code-duplication. Patches: 01-08: Preparation and movement of sev-guest driver code 09-16: SecureTSC enablement patches. Testing SecureTSC ----------------- SecureTSC hypervisor patches based on top of SEV-SNP Guest MEMFD series: https://github.com/AMDESE/linux-kvm/tree/sectsc-host-latest QEMU changes: https://github.com/nikunjad/qemu/tree/snp-securetsc-latest QEMU commandline SEV-SNP with SecureTSC: qemu-system-x86_64 -cpu EPYC-Milan-v2,+securetsc,+invtsc -smp 4 \ -object memory-backend-memfd,id=ram1,size=1G,share=true,prealloc=false,reserve=false \ -object sev-snp-guest,id=sev0,cbitpos=51,reduced-phys-bits=1,secure-tsc=on \ -machine q35,confidential-guest-support=sev0,memory-backend=ram1 \ ... Changelog: ---------- v8: * Rebased on top of tip/x86/sev * Use minimum size of IV or msg_seqno in memcpy * Use arch/x86/include/asm/sev.h instead of sev-guest.h * Use DEFINE_MUTEX for snp_guest_cmd_mutex * Added Reviewed-by from Tom. * Dropped Tested-by from patch 3/16 https://lore.kernel.org/kvm/20231220151358.2147066-1-nikunj@amd.com/ v7: * Drop mutex from the snp_dev and add snp_guest_cmd_{lock,unlock} API * Added comments for secrets page failure * Added define for maximum supported VMPCK * Updated comments why sev_status is used directly instead of cpu_feature_enabled() https://lore.kernel.org/kvm/20231220151358.2147066-1-nikunj@amd.com/ v6: https://lore.kernel.org/lkml/20231128125959.1810039-1-nikunj@amd.com/ v5: https://lore.kernel.org/lkml/20231030063652.68675-1-nikunj@amd.com/ v4: https://lore.kernel.org/lkml/20230814055222.1056404-1-nikunj@amd.com/ v3: https://lore.kernel.org/lkml/20230722111909.15166-1-nikunj@amd.com/ v2: https://lore.kernel.org/r/20230307192449.24732-1-bp@alien8.de/ v1: https://lore.kernel.org/r/20230130120327.977460-1-nikunj@amd.com Nikunj A Dadhania (16): virt: sev-guest: Use AES GCM crypto library virt: sev-guest: Replace dev_dbg with pr_debug virt: sev-guest: Add SNP guest request structure virt: sev-guest: Add vmpck_id to snp_guest_dev struct x86/sev: Cache the secrets page address virt: sev-guest: Move SNP Guest command mutex x86/sev: Move and reorganize sev guest request api x86/mm: Add generic guest initialization hook x86/cpufeatures: Add synthetic Secure TSC bit x86/sev: Add Secure TSC support for SNP guests x86/sev: Change TSC MSR behavior for Secure TSC enabled guests x86/sev: Prevent RDTSC/RDTSCP interception for Secure TSC enabled guests x86/kvmclock: Skip kvmclock when Secure TSC is available x86/sev: Mark Secure TSC as reliable x86/cpu/amd: Do not print FW_BUG for Secure TSC x86/sev: Enable Secure TSC for SNP guests arch/x86/Kconfig | 1 + arch/x86/boot/compressed/sev.c | 3 +- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/sev-common.h | 1 + arch/x86/include/asm/sev.h | 206 ++++++- arch/x86/include/asm/svm.h | 6 +- arch/x86/include/asm/x86_init.h | 2 + arch/x86/kernel/cpu/amd.c | 3 +- arch/x86/kernel/kvmclock.c | 2 +- arch/x86/kernel/sev-shared.c | 10 + arch/x86/kernel/sev.c | 648 +++++++++++++++++++-- arch/x86/kernel/x86_init.c | 2 + arch/x86/mm/mem_encrypt.c | 12 +- arch/x86/mm/mem_encrypt_amd.c | 12 + drivers/virt/coco/sev-guest/Kconfig | 3 - drivers/virt/coco/sev-guest/sev-guest.c | 725 ++++-------------------- drivers/virt/coco/sev-guest/sev-guest.h | 63 -- 17 files changed, 937 insertions(+), 763 deletions(-) delete mode 100644 drivers/virt/coco/sev-guest/sev-guest.h base-commit: ee8ff8768735edc3e013837c4416f819543ddc17 -- 2.34.1