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AJvYcCVkiiwK+4n0IEk0BtNh0+EIWBOvQ/bpn56e1oWzWEjLaNuif6NOJ7VeLe6IEGZjgE1B8Dx6V/llBFLAh5PBZ77MRpkVylJRsShQ7JcT X-Gm-Message-State: AOJu0YxXlr1zQdFiJwhiTtQp3FNGy0/d6/8RDTfE+o6YkPxiNArWjvdl HoZpm6IZSmkMZyOn7quSZ+wiNfe8qdfwQuiU7a3BVcnqR5oJy6NVFuvWgg3d2MM= X-Received: by 2002:a17:903:1212:b0:1d9:14fb:d142 with SMTP id l18-20020a170903121200b001d914fbd142mr3570668plh.32.1708042122114; Thu, 15 Feb 2024 16:08:42 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id bb6-20020a170902bc8600b001db3d365082sm1789486plb.265.2024.02.15.16.08.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Feb 2024 16:08:41 -0800 (PST) From: Samuel Holland To: Will Deacon , Mark Rutland , Eric Lin , Conor Dooley Cc: Palmer Dabbelt , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , linux-riscv@lists.infradead.org, Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, Samuel Holland Subject: [PATCH v1 1/6] dt-bindings: cache: Document the sifive,perfmon-counters property Date: Thu, 15 Feb 2024 16:08:13 -0800 Message-ID: <20240216000837.1868917-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240216000837.1868917-1-samuel.holland@sifive.com> References: <20240216000837.1868917-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The SiFive Composable Cache controller contains an optional PMU with a configurable number of event counters. Document a property which describes the number of available counters. Signed-off-by: Samuel Holland --- Documentation/devicetree/bindings/cache/sifive,ccache0.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml index 7e8cebe21584..100eda4345de 100644 --- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml +++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml @@ -81,6 +81,11 @@ properties: The reference to the reserved-memory for the L2 Loosely Integrated Memory region. The reserved memory node should be defined as per the bindings in reserved-memory.txt. + sifive,perfmon-counters: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + description: Number of PMU counter registers + allOf: - $ref: /schemas/cache-controller.yaml# -- 2.43.0