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Thu, 15 Feb 2024 17:07:32 -0800 Date: Thu, 15 Feb 2024 17:07:30 -0800 From: Nicolin Chen To: Robin Murphy CC: Keith Busch , , , , , , , , , , , Subject: Re: [PATCH v1 2/2] nvme-pci: Fix iommu map (via swiotlb) failures when PAGE_SIZE=64KB Message-ID: References: <60bdcc29a2bcf12c6ab95cf0ea480d67c41c51e7.1707851466.git.nicolinc@nvidia.com> <7f14727d-3ca6-45ec-9251-f166f74a8f7c@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <7f14727d-3ca6-45ec-9251-f166f74a8f7c@arm.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF00003445:EE_|CYXPR12MB9317:EE_ X-MS-Office365-Filtering-Correlation-Id: 0608099c-c4cd-4081-45b5-08dc2e8baf4c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: VU0HZoThP4exs1AONdOHmOteR+RBE23sr7UunZAsinLwg7EA15+6k6/FYvq8vpGk6JYysVk1jwqoBj/jWpvLJZHg/ekyz8/sMFEQgJr5KfUvpFy3y6AtBhYC4gaJVN/pAICIv2SOQJRECnX0RppZSN0JyejfRnQ56pp1Pyjk83o494A/yZKPaOdp7C4K99gpeyVEuBZL7GiXDNi2PWkZBgpXQjzhFDyUsxaSBaUS2uFHd4xjMEDTmwFDMUjel7771+iCKhrIPPR+6BTdBgehsdu6XfyekUv8ysv2dp7cyoQqSn8cQKNdqoPaN//1YpTo5ObSqBEGDoetjEqFXlqpehgh/7XRQjKQ+X88Uzo4ZSVIJ6edy94i1jTIn/F0AkIMKcXqZRPFX1re4eERIAg21LkKbvcxQ2hMVUeUToTypjr5opvbJnnHpU5iq6sLmpWFKih4biutY8qmrimgcqVdew2Nv/MVRbzFqhAbP0cVcsmwRP6qopdSi0mc27sjP0Ep4zp5eCvm5eN82QYbpTgExeQjIgMkS53hYRvHeiJXKB8hQmw6rZbmJgB+S+hYFTuDx4NGEvfOgFN+XGiJFaiJkFmvD6gGZL8TCEsVybBKCZLM01OkGoWg3Aigd0qEDpSJCUR/OEub1JMZ/6kqNhDtUhSJwCnnKkpC1Y0XcMdZLxM= X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(346002)(396003)(39860400002)(230922051799003)(82310400011)(1800799012)(451199024)(64100799003)(36860700004)(186009)(46966006)(40470700004)(336012)(316002)(86362001)(33716001)(83380400001)(6916009)(70586007)(53546011)(9686003)(82740400003)(478600001)(5660300002)(7416002)(7636003)(426003)(54906003)(70206006)(2906002)(26005)(4326008)(8936002)(356005)(8676002)(41300700001)(55016003);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Feb 2024 01:07:45.4704 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0608099c-c4cd-4081-45b5-08dc2e8baf4c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF00003445.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYXPR12MB9317 On Thu, Feb 15, 2024 at 12:01:34PM +0000, Robin Murphy wrote: > On 15/02/2024 4:46 am, Nicolin Chen wrote: > > On Wed, Feb 14, 2024 at 06:36:38PM -0700, Keith Busch wrote: > > > On Tue, Feb 13, 2024 at 10:09:19PM -0800, Nicolin Chen wrote: > > > > On Tue, Feb 13, 2024 at 04:31:04PM -0700, Keith Busch wrote: > > > > > On Tue, Feb 13, 2024 at 01:53:57PM -0800, Nicolin Chen wrote: > > > > > > @@ -2967,7 +2967,7 @@ static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, > > > > > > dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); > > > > > > else > > > > > > dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); > > > > > > - dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); > > > > > > + dma_set_min_align_mask(&pdev->dev, PAGE_SIZE - 1); > > > > > > dma_set_max_seg_size(&pdev->dev, 0xffffffff); > > > > > > > > > > I recall we had to do this for POWER because they have 64k pages, but > > > > > page aligned addresses IOMMU map to 4k, so we needed to allow the lower > > > > > dma alignment to efficiently use it. > > > > > > > > Thanks for the input! > > > > > > > > In that case, we might have to rely on iovad->granule from the > > > > attached iommu_domain: > > > > > > I explored a bit more, and there is some PPC weirdness that lead to > > > NVME_CTRL_PAGE_SIZE, I don't find the dma min align mask used in that > > > path. It looks like swiotlb is the only user for this, so your original > > > patch may be just fine. > > > > Oh, that'll be great if we confirmed. And I think I forgot to add > > CC line to the stable trees: the two patches should be applicable > > cleanly to older kernels too. Let's wait for some day, so people > > can give some tests and reviews. Then I will respin a v2 with the > > CC line. > > Hmm, as far as I understand, NVME_CTRL_PAGE_SIZE represents the > alignment that NVMe actually cares about, so if specifying that per the > intended purpose of the API doesn't work then it implies the DMA layer > is still not doing its job properly, thus I'd rather keep digging and > try to fix that properly. > > FWIW I have a strong suspicion that iommu-dma may not be correctly doing > what it thinks it's trying to do, so I would definitely think it > worthwhile to give that a really close inspection in light of Will's > SWIOTLB fixes. Yes. Let's figure out what's breaking Will's change. Thanks Nicolin