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From: =?UTF-8?Q?Pawe=C5=82_Owoc?= <frut3k7@gmail.com>
Date: Fri, 16 Feb 2024 14:39:19 +0100
Message-ID: <CAKEyCaD=2Md8f=K0pfAFmSCQjL0PkBvAzG_g5Me-wpd5iv2rVw@mail.gmail.com>
Subject: Re: [PATCH v2 2/2] dt-bindings: trivial-devices: Add qca,qca4024
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>, Robert Marko <robimarko@gmail.com>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Mark Brown <broonie@kernel.org>, Guenter Roeck <linux@roeck-us.net>, 
	Peter Yin <peteryin.openbmc@gmail.com>, 
	Patrick Rudolph <patrick.rudolph@9elements.com>, Michal Simek <michal.simek@amd.com>, 
	Marek Vasut <marex@denx.de>, Luca Ceresoli <luca.ceresoli@bootlin.com>, 
	Bjorn Helgaas <bhelgaas@google.com>, Lukas Wunner <lukas@wunner.de>, Fabio Estevam <festevam@denx.de>, 
	Alexander Stein <alexander.stein@ew.tq-group.com>, devicetree@vger.kernel.org, 
	linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org
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To be clear, I don't want to add support for the QCA4024, I just want
to use this SoC with its own firmware connected to another SoC
(IPQ8072A) via spi.

On Fri, Feb 16, 2024 at 8:19=E2=80=AFAM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 15/02/2024 23:01, frut3k7 wrote:
> > The device I use has the QCA4024 chip connected via the spi controller:
> >         blsp1_spi4: spi@78b8000 {
> >             compatible =3D "qcom,spi-qup-v2.2.1";
> >             #address-cells =3D <1>;
> >             #size-cells =3D <0>;
> >             reg =3D <0x78b8000 0x600>;
> >             interrupts =3D <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> >             clocks =3D <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
> >                  <&gcc GCC_BLSP1_AHB_CLK>;
> >             clock-names =3D "core", "iface";
> >             dmas =3D <&blsp_dma 18>, <&blsp_dma 19>;
> >             dma-names =3D "tx", "rx";
> >             status =3D "disabled";
> >         };
> >
> > and apart from setting the frequency and gpio there is nothing else:
> >         &blsp1_spi4 {
> >             status =3D "okay";
> >
> >             pinctrl-0 =3D <&spi_3_pins &quartz_pins>;
> >             pinctrl-names =3D "default";
> >
> >             /* Qualcomm QCA4024 IoT */
> >             iot@3 {
> >                 compatible =3D "qca,qca4024";
> >                 reg =3D <0>;
> >                 spi-max-frequency =3D <24000000>;
>
> That's your downstream or fork DTS, not hardware description. You could
> have several regulators not listed here, because your downstream has
> always-on, or clocks which are not taken and works due to
> assigned-clocks in other places... Sorry, that's not an argument. Never
> use downstream DTS as proof how hardware looks. It is usually dis-proof,
> that things are certainly missing.
>
> Best regards,
> Krzysztof
>