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bh=JPbrPrP1ijVSXKNmyURydafvZaHC6pe91ZQgbIkuRYc=; b=cfQGC+s2whq7zOLn+SMUOtrmFy7nn9LZb4H0T3laC5F/x/WtTZKtUK7X uGIeXnmtNRYclVQiX6jxW8iKD4Nhmb5HlBskLdvGqI/0l6gwz8BjFr8WM ZmRAem2sRAK19oy+zW+mbQaRl9aN5XlEGrIdcmtAwX2ZHAUSzHRfY0Ocz pxBpQvYKwJfKtIr9chZp0kexg2HOjVyBj9Q+Q4rIr8H0mwnY/NelFhRHc WA3EEKaQl0es+jtjPQ2wWwLPt38EfqLppXefIwILZiJrBL6H3A1UBBmLv PoeKF0rI1u3Wl5L3dXVDJefohW15ritt3OTNNXfNBmEBcgnRiWLRvpW0V w==; X-IronPort-AV: E=McAfee;i="6600,9927,10986"; a="6018250" X-IronPort-AV: E=Sophos;i="6.06,165,1705392000"; d="scan'208";a="6018250" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2024 09:53:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,165,1705392000"; d="scan'208";a="4180210" Received: from bfraley-mobl.amr.corp.intel.com (HELO [10.209.109.53]) ([10.209.109.53]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Feb 2024 09:53:40 -0800 Message-ID: <93c91582-ae3b-47a6-98f8-d3a7cf74313e@linux.intel.com> Date: Fri, 16 Feb 2024 09:53:39 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] PCI: Increase maximum PCIe physical function number to 7 for non-ARI devices Content-Language: en-US To: Bean Huo , bhelgaas@google.com, schnelle@linux.ibm.com Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Bean Huo References: <20240216172449.8052-1-beanhuo@iokpp.de> From: Kuppuswamy Sathyanarayanan In-Reply-To: <20240216172449.8052-1-beanhuo@iokpp.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2/16/24 9:24 AM, Bean Huo wrote: > From: Bean Huo > > The PCIe specification allows up to 8 Physical Functions (PFs) per endpoint > when ARI (Alternative Routing-ID Interpretation) is not supported. Previously, > our implementation erroneously limited the maximum number of PFs to 7 for > endpoints without ARI support. Can you include the spec section and revision details? I assume it is section "Alternative Routing-ID Interpretation" > > This patch corrects the maximum PF count to adhere to the PCIe specification > by allowing up to 8 PFs on non-ARI endpoints. This change ensures better > compliance with the standard and improves compatibility with devices relying > on this specification. > > This adjustment was verified against the PCIe spec (reference specific > sections if applicable) and tested with a range of PCIe devices not supporting > ARI to ensure no regressions in functionality. > > Signed-off-by: Bean Huo > --- Since it is a bug fix, I think you need a Fixes: tag as well. > drivers/pci/probe.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c > index ed6b7f48736a..8c3d0f63bc13 100644 > --- a/drivers/pci/probe.c > +++ b/drivers/pci/probe.c > @@ -2630,7 +2630,8 @@ static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) > if (pci_ari_enabled(bus)) > return next_ari_fn(bus, dev, fn); > > - if (fn >= 7) > + /* If EP does not support ARI, the maximum number of functions should be 7 */ > + if (fn > 7) > return -ENODEV; > /* only multifunction devices may have more functions */ > if (dev && !dev->multifunction) -- Sathyanarayanan Kuppuswamy Linux Kernel Developer