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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708116611; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/MiNcyV6cuA2bEaO9pcAB0n2lgB9jPzAIMw9Rcvipmc=; b=IHl9ORoCzIXPoV6LABWoXZZeMThG96CoIBAQQ027SKATZEF6fDtWiZ+bTW4kAY8lPa27DL Eo4oTrIMRPfMUn84ibsglx2TpDLUv3K0b85/SkLNV1z+KsIqNFC7n0oEiMVgIxu87uW7SM gvkoKgs9jvUqkGi9yLTP7IWTTMRVxzGIMhqUE2sUzhakn9LAeuR0LULqYWkqRFEWvIasLv EUrOGTu9obLyx99g44CXIknPz4XE1ItIo56xNMLgDlofUnnpx2GK7jbWIUKgbTBEzntOXN hNXXARggoTtPidzCj/D3DyFrgc7uETU2mjLp+kb+XMhpRhqnHgMsYlzQq7YGSg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708116611; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=/MiNcyV6cuA2bEaO9pcAB0n2lgB9jPzAIMw9Rcvipmc=; b=UQZ1bO66o3f1pXva2taPAXPSKlpKkqJV7Ezk94IO8xuYtdCOe4hdhfUQZY8wcsbasEmJJ8 cRHlhm4HLiyx/WCw== To: Anup Patel , Palmer Dabbelt , Paul Walmsley , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: Re: [PATCH v12 22/25] irqchip: Add RISC-V advanced PLIC driver for direct-mode In-Reply-To: <20240127161753.114685-23-apatel@ventanamicro.com> References: <20240127161753.114685-1-apatel@ventanamicro.com> <20240127161753.114685-23-apatel@ventanamicro.com> Date: Fri, 16 Feb 2024 21:50:10 +0100 Message-ID: <875xyocewt.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Sat, Jan 27 2024 at 21:47, Anup Patel wrote: > +static int aplic_direct_irqdomain_translate(struct irq_domain *d, > + struct irq_fwspec *fwspec, > + unsigned long *hwirq, > + unsigned int *type) Please align the arguments to the first argument of the first line and use the 100 characters, i.e. static int aplic_direct_irqdomain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) { All over the place. > +{ > + struct aplic_priv *priv = d->host_data; > + > + return aplic_irqdomain_translate(fwspec, priv->gsi_base, > + hwirq, type); > +} > + > +static int aplic_direct_irqdomain_alloc(struct irq_domain *domain, > + unsigned int virq, unsigned int nr_irqs, > + void *arg) > +{ > + int i, ret; > + unsigned int type; > + irq_hw_number_t hwirq; > + struct irq_fwspec *fwspec = arg; > + struct aplic_priv *priv = domain->host_data; > + struct aplic_direct *direct = > + container_of(priv, struct aplic_direct, priv); Variable ordering. Please make this consistent according to documentation. > + ret = aplic_irqdomain_translate(fwspec, priv->gsi_base, > + &hwirq, &type); > + if (ret) > + return ret; > + > + for (i = 0; i < nr_irqs; i++) { > + irq_domain_set_info(domain, virq + i, hwirq + i, > + &aplic_direct_chip, priv, > + handle_fasteoi_irq, NULL, NULL); > + irq_set_affinity(virq + i, &direct->lmask); > + /* See the reason described in aplic_msi_irqdomain_alloc() */ I still have to understand that "reason". :) > + irq_set_status_flags(virq + i, IRQ_DISABLE_UNLAZY); > + } Thanks, tglx