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Sun, 18 Feb 2024 09:43:46 GMT Received: from hu-jinlmao-lv.qualcomm.com (10.49.16.6) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Sun, 18 Feb 2024 01:43:46 -0800 From: Mao Jinlong To: Suzuki K Poulose , Mike Leach , James Clark , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Mao Jinlong" , Tao Zhang , Alexander Shishkin CC: , , , , Subject: [PATCH v3 1/2] dt-bindings: arm: qcom,coresight-tpdm: Rename qcom,dsb-element-size Date: Sun, 18 Feb 2024 01:43:19 -0800 Message-ID: <20240218094322.22470-2-quic_jinlmao@quicinc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240218094322.22470-1-quic_jinlmao@quicinc.com> References: <20240218094322.22470-1-quic_jinlmao@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xlUXZiqKJrL5z87HpcIp1MVdpiXfESS5 X-Proofpoint-ORIG-GUID: xlUXZiqKJrL5z87HpcIp1MVdpiXfESS5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-18_07,2024-02-16_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 mlxlogscore=984 lowpriorityscore=0 priorityscore=1501 adultscore=0 malwarescore=0 impostorscore=0 spamscore=0 mlxscore=0 bulkscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402180073 Change qcom,dsb-element-size to qcom,dsb-element-bits as the unit is bit. There is no tpdm node in any DT as of now. Make this change before any tpdm node is added to DT. Fixes: 2a8d9b371566 ("dt-bindings: arm: Add support for DSB element size") Signed-off-by: Mao Jinlong --- .../devicetree/bindings/arm/qcom,coresight-tpdm.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml index d0647ffaed71..8eec07d9d454 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml @@ -44,12 +44,11 @@ properties: minItems: 1 maxItems: 2 - qcom,dsb-element-size: + qcom,dsb-element-bits: description: Specifies the DSB(Discrete Single Bit) element size supported by the monitor. The associated aggregator will read this size before it is enabled. DSB element size currently only supports 32-bit and 64-bit. - $ref: /schemas/types.yaml#/definitions/uint8 enum: [32, 64] qcom,cmb-element-bits: @@ -111,7 +110,7 @@ examples: compatible = "qcom,coresight-tpdm", "arm,primecell"; reg = <0x0684c000 0x1000>; - qcom,dsb-element-size = /bits/ 8 <32>; + qcom,dsb-element-bits = <32>; qcom,dsb-msrs-num = <16>; clocks = <&aoss_qmp>; -- 2.41.0