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From: Daniel Mentz <danielmentz@google.com>
Date: Sun, 18 Feb 2024 21:44:47 -0800
Message-ID: <CAE2F3rA1Lb_ayrLQTw+urtNSMoBg9q6CmcSsP7_dZwbfiYygsw@mail.gmail.com>
Subject: Re: [PATCH] drivers/iommu: Ensure that the queue base address is
 successfully written during SMMU initialization.
To: "ni.liqiang" <niliqiang.io@gmail.com>
Cc: Will Deacon <will@kernel.org>, Robin Murphy <robin.murphy@arm.com>, 
	Joerg Roedel <joro@8bytes.org>, "jin . qi" <jin.qi@zte.com.cn>, 
	linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, 
	linux-kernel@vger.kernel.org
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On Sat, Feb 17, 2024 at 9:02=E2=80=AFPM ni.liqiang <niliqiang.io@gmail.com>=
 wrote:
> If there are no memory barriers, how can we ensure this order?

 The SMMU registers are accessed using Device-nGnRE attributes. It is
my understanding that, for Device-nGnRE, the Arm architecture requires
that writes to the same peripheral arrive at the endpoint in program
order.