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[209.85.128.176]) by smtp.gmail.com with ESMTPSA id b1-20020a0dd901000000b005ffa352a84fsm1532120ywe.21.2024.02.19.00.49.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Feb 2024 00:49:06 -0800 (PST) Received: by mail-yw1-f176.google.com with SMTP id 00721157ae682-608245e549fso9515247b3.1; Mon, 19 Feb 2024 00:49:06 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCWfZracA1pCHPIVKpGKmWryvuLuLucaE0zDhEYAij9TvPNWSFxJaq/jJ0G1bzL48pe2jtPcDEs3UezWQuFCDNxTPTOhWrUoM3HChFDK+0O5RpJPbDqhGxTlPl3CTxCK9EpsXqwrGcQrI4Yu8FCeLaIEXt88Y/BR/GOX0u0oWZ+84hwW3oFJMO+Qw0ILvRE5k7Xmp5hqWY9IdIIMr+Pn3iKXkv8YB/jp X-Received: by 2002:a05:690c:a16:b0:608:28a9:5cfb with SMTP id cg22-20020a05690c0a1600b0060828a95cfbmr2721260ywb.16.1708332545819; Mon, 19 Feb 2024 00:49:05 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> <20240208124300.2740313-8-claudiu.beznea.uj@bp.renesas.com> <4098873b-a7e7-4c88-9af2-01f3c76424ab@tuxon.dev> In-Reply-To: <4098873b-a7e7-4c88-9af2-01f3c76424ab@tuxon.dev> From: Geert Uytterhoeven Date: Mon, 19 Feb 2024 09:48:53 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 07/17] clk: renesas: rzg2l: Extend power domain support To: claudiu beznea Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Claudiu, On Mon, Feb 19, 2024 at 9:24=E2=80=AFAM claudiu beznea wrote: > On 16.02.2024 16:08, Geert Uytterhoeven wrote: > > On Thu, Feb 8, 2024 at 1:44=E2=80=AFPM Claudiu wrote: > >> From: Claudiu Beznea > >> > >> RZ/{G2L, V2L, G3S}-based CPG versions have support for saving extra > >> power when clocks are disabled by activating module standby. This is d= one > >> through MSTOP-specific registers that are part of CPG. Each individual > >> module has one or more bits associated with one MSTOP register (see ta= ble > >> "Registers for Module Standby Mode" from HW manuals). Hardware manual > >> associates modules' clocks with one or more MSTOP bits. There are 3 ma= ppings > >> available (identified by researching RZ/G2L, RZ/G3S, RZ/V2L HW manuals= ): > >> > >> case 1: N clocks mapped to N MSTOP bits (with N=3D{0, ..., X}) > >> case 2: N clocks mapped to 1 MSTOP bit (with N=3D{0, ..., X}) > >> case 3: N clocks mapped to M MSTOP bits (with N=3D{0, ..., X}, M=3D{0,= ..., Y}) > >> > >> Case 3 has been currently identified on RZ/V2L for the VCPL4 module. > >> > >> To cover all three cases, the individual platform drivers will provide= to > >> clock driver MSTOP register offset and associated bits in this registe= r > >> as a bitmask and the clock driver will apply this bitmask to proper > >> MSTOP register. > >> > >> Apart from MSTOP support, RZ/G3S can save more power by powering down = the > >> individual IPs (after MSTOP has been set) if proper bits in > >> CPG_PWRDN_IP{1,2} registers are set. > >> > >> The MSTOP and IP power down support were implemented through power > >> domains. Platform-specific clock drivers will register an array of > >> type struct rzg2l_cpg_pm_domain_init_data, which will be used to > >> instantiate properly the power domains. > >> > >> Signed-off-by: Claudiu Beznea > > > > Thanks for your patch! > > > >> --- a/drivers/clk/renesas/rzg2l-cpg.c > >> +++ b/drivers/clk/renesas/rzg2l-cpg.c > >> @@ -1559,9 +1556,34 @@ static bool rzg2l_cpg_is_pm_clk(struct rzg2l_cp= g_priv *priv, > >> return true; > >> } > [ ... ] > > > > >> @@ -234,6 +246,54 @@ struct rzg2l_reset { > >> #define DEF_RST(_id, _off, _bit) \ > >> DEF_RST_MON(_id, _off, _bit, -1) > >> > >> +/** > >> + * struct rzg2l_cpg_pm_domain_conf - PM domain configuration data str= ucture > >> + * @mstop: MSTOP configuration (MSB =3D register offset, LSB =3D bitm= ask) > >> + * @pwrdn: PWRDN configuration (MSB =3D register offset, LSB =3D regi= ster bit) > >> + */ > >> +struct rzg2l_cpg_pm_domain_conf { > >> + u32 mstop; > >> + u32 pwrdn; > > > > Why not > > > > u16 mstop_off; > > u16 mstop_mask; > > u16 pwrdn_off; > > u16 pwrdn_mask; > > > > so you can drop the MSTOP*() and PWRDN*() macros below? > > I did it like this to align with the already existing approach for this > kind of things available in this driver. I can do it as you proposed. The other fields do not align nicely with byte or word boundaries. I can see the value of the MSTOP(name, bitmask) and PWRDN(name, bitmask) macros, but I'd rather get rid of the *_MASK() and *_OFF() variants. > For the rest of your comments on this patch: I agree and will adjust the > patch in the next version. Thanks! Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds