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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR12MB7199.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8a061421-59cf-43c6-0b0f-08dc312e3e60 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Feb 2024 09:36:26.4475 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: JN19g+Mjaq3PNcxunR0eToRyBfiZvCsIIQHGySDzJMAhe70SOyOyyiLjya2JfKIxs+TiDoYK9uM6z7MjdySWjg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5775 >> diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c=0A= >> b/drivers/vfio/pci/nvgrace-gpu/main.c new file mode 100644=0A= >> index 000000000000..5a251a6a782e=0A= >> --- /dev/null=0A= >> +++ b/drivers/vfio/pci/nvgrace-gpu/main.c=0A= >> @@ -0,0 +1,888 @@=0A= >> +// SPDX-License-Identifier: GPL-2.0-only=0A= >> +/*=0A= >> + * Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights=0A= >> reserved=0A= >> + */=0A= >> +=0A= >> +#include =0A= >> +#include =0A= >> +=0A= >=0A= > Let's keep the header inclusion in an alphabet order.=0A= >=0A= > With that addressed,=0A= >=0A= > Reviewed-by: Zhi Wang =0A= =0A= Yes, will adjust that. Thanks!=0A= =0A= >> +/*=0A= >> + * The device memory usable to the workloads running in the VM is=0A= >> cached=0A= >> + * and showcased as a 64b device BAR (comprising of BAR4 and BAR5=0A= >> region)=0A= >> + * to the VM and is represented as usemem.=0A= >> + * Moreover, the VM GPU device driver needs a non-cacheable region to= =0A= >> + * support the MIG feature. This region is also exposed as a 64b BAR=0A= >> + * (comprising of BAR2 and BAR3 region) and represented as resmem.=0A= >> + */=0A= >> +#define RESMEM_REGION_INDEX VFIO_PCI_BAR2_REGION_INDEX=0A= >> +#define USEMEM_REGION_INDEX VFIO_PCI_BAR4_REGION_INDEX=0A=