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charset=us-ascii Content-Disposition: inline In-Reply-To: <1708107297-1798828-1-git-send-email-radhey.shyam.pandey@amd.com> On Fri, Feb 16, 2024 at 11:44:57PM +0530, Radhey Shyam Pandey wrote: > Platform clock and phy error resources are not cleaned up in Xilinx GT PHY > error path. > > To fix introduce the function ceva_ahci_platform_enable_resources() which > is a customized version of ahci_platform_enable_resources() and inline with > SATA IP programming sequence it does: > > - Assert SATA reset > - Program PS GTR phy > - Bring SATA by de-asserting the reset > - Wait for GT lane PLL to be locked > > ceva_ahci_platform_enable_resources() is also used in the resume path > as the same SATA programming sequence (as in probe) should be followed. > Also cleanup the mixed usage of ahci_platform_enable_resources() and custom > implementation in the probe function as both are not required. > > Fixes: 9a9d3abe24bb ("ata: ahci: ceva: Update the driver to support xilinx GT phy") > Signed-off-by: Radhey Shyam Pandey > Reviewed-by: Damien Le Moal > --- > Changes for v3: > - Modified commit description as suggested by Damien Le Moal. > - Add missing return in dev_err_probe("failed to get reset") > pointed by Niklas. > > Changes for v2: > > - Create wrapper ceva_ahci_platform_enable_resources() > - Remove legacy ahci_platform_enable_resources() and its related code. > - Modified commit description and merge 1/2 and 2/2 fix as it is > automatically done when reusing ahci_platform_enable_resources() > logic. > - Drop Reviewed-by: Damien Le Moal tag. > --- Applied: https://git.kernel.org/pub/scm/linux/kernel/git/libata/linux.git/log/?h=for-6.8-fixes