Received-SPF: pass (google.com: domain of linux-kernel+bounces-71136-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3;
Received-SPF: Fail (protection.outlook.com: domain of axis.com does not
 designate 195.60.68.100 as permitted sender) receiver=protection.outlook.com;
 client-ip=195.60.68.100; helo=mail.axis.com;
Date: Mon, 19 Feb 2024 11:40:25 +0100
From: Jesper Nilsson <jesper.nilsson@axis.com>
To: Florian Fainelli <f.fainelli@gmail.com>
CC: Jesper Nilsson <jesper.nilsson@axis.com>, Alexandre Torgue
	<alexandre.torgue@foss.st.com>, Jose Abreu <joabreu@synopsys.com>, "David S.
 Miller" <davem@davemloft.net>, Eric Dumazet <edumazet@google.com>, "Jakub
 Kicinski" <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>, Maxime Coquelin
	<mcoquelin.stm32@gmail.com>, <netdev@vger.kernel.org>,
	<linux-stm32@st-md-mailman.stormreply.com>,
	<linux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
	<kernel@axis.com>
Subject: Re: [PATCH] net: stmmac: mmc_core: Assign, don't add interrupt
 registers
Message-ID: <20240219104025.GM22484@axis.com>
References: <20240216-stmmac_stats-v1-1-7065fa4613f8@axis.com>
 <61bdd802-abe4-4544-8e48-9493a6bb99c8@gmail.com>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Disposition: inline
In-Reply-To: <61bdd802-abe4-4544-8e48-9493a6bb99c8@gmail.com>
User-Agent: Mutt/1.10.1 (2018-07-13)
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Feb 2024 10:40:26.3556
 (UTC)
X-MS-Exchange-CrossTenant-Network-Message-Id: 7ee31ed9-da99-4c0e-3369-08dc31372f49
X-MS-Exchange-CrossTenant-Id: 78703d3c-b907-432f-b066-88f7af9ca3af
X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=78703d3c-b907-432f-b066-88f7af9ca3af;Ip=[195.60.68.100];Helo=[mail.axis.com]
X-MS-Exchange-CrossTenant-AuthSource:
	AM2PEPF0001C716.eurprd05.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Anonymous
X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem
X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR02MB6511

On Fri, Feb 16, 2024 at 09:13:51AM -0800, Florian Fainelli wrote:
> So in premise I agree with the patch, that incrementing those is not the
> right way to go about them. However these registers are currently provided
> as part of the statistics set, but they should instead be accessed via the
> register dumping method.

You mean extending the dump register code to dump the MAC Management Counter
registers that are not counters?
From what I understand it's only the Rx and Tx interrupt and interrupt mask
registers that aren't counters. Oh, and the MMC control register itself?

To be honest, I don't think their use can justify the code churn.

> In either case you will get at best a snapshot of those two registers at any
> given time and I suppose this can help diagnose a stuck RX condition, but
> not much more than that.

Yeah, their use is very doubtful. For me, they only introduce more nonsense
data in my logs.

The Rx registers looks to have been added in the first version of the MMC
back in 2011, but the Tx registers never was.
In commit 1c901a46d57 Giuseppe mentions the MMC interrupts as something to
add later (if actually useful).

So Serge's suggestion to drop the entries completely is actually quite attractive.

> Florian

/^JN - Jesper Nilsson
-- 
               Jesper Nilsson -- jesper.nilsson@axis.com