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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiner Kallweit , Russell King , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH net-next v3 3/6] net: hisilicon: add support for hisi_femac core on Hi3798MV200 Message-ID: <29fc21f0-0e46-4d0f-8d4b-c4dbd1689c55@lunn.ch> References: <20240220-net-v3-0-b68e5b75e765@outlook.com> <20240220-net-v3-3-b68e5b75e765@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240220-net-v3-3-b68e5b75e765@outlook.com> > Note it's unable to put the MDIO bus node outside of MAC controller > (i.e. at the same level in the parent bus node). Because we need to > control all clocks and resets in FEMAC driver due to the phy reset > procedure. So the clocks can't be assigned to MDIO bus device, which is > an essential resource for the MDIO bus to work. What PHY driver is being used? If there a specific PHY driver for this hardware? Does it implement soft reset? I'm wondering if you can skip hardware reset of the PHY and only do a software reset. Andrew