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Mon, 19 Feb 2024 21:27:59 +0000 (UTC) From: Yang Xiwen via B4 Relay Date: Tue, 20 Feb 2024 05:28:00 +0800 Subject: [PATCH RFC v3 3/5] phy: hisilicon: hisi-inno-phy: enable clocks for every ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240220-inno-phy-v3-3-893cdf8633b4@outlook.com> References: <20240220-inno-phy-v3-0-893cdf8633b4@outlook.com> In-Reply-To: <20240220-inno-phy-v3-0-893cdf8633b4@outlook.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jiancheng Xue , Shawn Guo , Philipp Zabel Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , David Yang , Yang Xiwen X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1708378078; l=971; i=forbidden405@outlook.com; s=20230724; h=from:subject:message-id; bh=jGUbESXsyAvU27nkXjLoTOKtwqcjOT068eM8RNJCWfs=; b=zs3Pye2H9yxnBHI/KFOaUXuqr2aivy0VIlFkP7na/Xbw3rIoaMubBcpeDNsVhE3207LPYz72J c2VRW0Hg+5MCQr8XwdaAjcx1MiDv9f2A/+Fv+yagKFNF/ujcU467b1S X-Developer-Key: i=forbidden405@outlook.com; a=ed25519; pk=qOD5jhp891/Xzc+H/PZ8LWVSWE3O/XCQnAg+5vdU2IU= X-Endpoint-Received: by B4 Relay for forbidden405@outlook.com/20230724 with auth_id=67 X-Original-From: Yang Xiwen Reply-To: From: Yang Xiwen This is needed for port1 to work. Fixes: ba8b0ee81fbb ("phy: add inno-usb2-phy driver for hi3798cv200 SoC") Signed-off-by: Yang Xiwen --- drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c index c138cd4807d6..b7e740eb4752 100644 --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c @@ -86,8 +86,10 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv, static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv) { + int i; /* The phy clk is controlled by the port0 register 0x06. */ - hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE); + for (i = 0; i < INNO_PHY_PORT_NUM; i++) + hisi_inno_phy_write_reg(priv, i, 0x06, PHY_CLK_ENABLE); msleep(PHY_CLK_STABLE_TIME); } -- 2.43.0