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From: Guo Ren <guoren@kernel.org>
Date: Tue, 20 Feb 2024 09:11:59 +0800
Message-ID: <CAJF2gTTW_bBwWAfNhiUNXpseg44fd_+=3j4NjCaqryzWN_194A@mail.gmail.com>
Subject: Re: [PATCH] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
To: Yangyu Chen <cyy@cyyself.name>
Cc: linux-riscv@lists.infradead.org, Jisheng Zhang <jszhang@kernel.org>, 
	Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Alexandre Ghiti <alexghiti@rivosinc.com>, linux-kernel@vger.kernel.org
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On Tue, Feb 20, 2024 at 12:33=E2=80=AFAM Yangyu Chen <cyy@cyyself.name> wro=
te:
>
> Previous commit dbfbda3bd6bf("riscv: mm: update T-Head memory type
> definitions") missed a `<` for bit shifting, result in bit[61] does not s=
et
> in _PAGE_NOCACHE_THEAD and leaves bit[0] set instead. This patch get this
> fixed.
>
> Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@k=
ernel.org/ [1]
>
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> ---
>  arch/riscv/include/asm/pgtable-64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm=
/pgtable-64.h
> index b42017d76924..b99bd66107a6 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -136,7 +136,7 @@ enum napot_cont_order {
>   * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareab=
le, Non-trustable
>   */
>  #define _PAGE_PMA_THEAD                ((1UL << 62) | (1UL << 61) | (1UL=
 << 60))
> -#define _PAGE_NOCACHE_THEAD    ((1UL < 61) | (1UL << 60))
> +#define _PAGE_NOCACHE_THEAD    ((1UL << 61) | (1UL << 60))
>  #define _PAGE_IO_THEAD         ((1UL << 63) | (1UL << 60))
>  #define _PAGE_MTMASK_THEAD     (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL =
<< 59))
>
> --
> 2.43.0
>

Oh, my genius. Thank you very much.

Reviewed-by: Guo Ren <guoren@kernel.org>

It's for bufferable signal, so that is why it does not affect the hardware =
:P

--=20
Best Regards
 Guo Ren