Received-SPF: pass (google.com: domain of linux-kernel+bounces-72171-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1;
Precedence: bulk
MIME-Version: 1.0
References: <cover.1708223519.git.unicorn_wang@outlook.com> <dc899c89e5c30e2267965f185b52d6dded4eb1ac.1708223519.git.unicorn_wang@outlook.com>
In-Reply-To: <dc899c89e5c30e2267965f185b52d6dded4eb1ac.1708223519.git.unicorn_wang@outlook.com>
From: Guo Ren <guoren@kernel.org>
Date: Tue, 20 Feb 2024 09:18:03 +0800
Message-ID: <CAJF2gTRPU6-8Wwds=PRREjU3W0cmCpBcc=w7=J9p_y+XSd3o6w@mail.gmail.com>
Subject: Re: [PATCH v10 5/5] riscv: dts: add clock generator for Sophgo SG2042 SoC
To: Chen Wang <unicornxw@gmail.com>
Cc: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, 
	krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, 
	palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, 
	robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, 
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, 
	linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, 
	xiaoguang.xing@sophgo.com, jszhang@kernel.org, inochiama@outlook.com, 
	samuel.holland@sifive.com, Chen Wang <unicorn_wang@outlook.com>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Sun, Feb 18, 2024 at 10:52=E2=80=AFAM Chen Wang <unicornxw@gmail.com> wr=
ote:
>
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add clock generator node to device tree for SG2042, and enable clock for
> uart.
>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 12 +++++
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi        | 48 +++++++++++++++++++
>  2 files changed, 60 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/r=
iscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> index 49b4b9c2c101..80cb017974d8 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
> @@ -14,6 +14,18 @@ chosen {
>         };
>  };
>
> +&cgi_main {
> +       clock-frequency =3D <25000000>;
> +};
> +
> +&cgi_dpll0 {
> +       clock-frequency =3D <25000000>;
> +};
> +
> +&cgi_dpll1 {
> +       clock-frequency =3D <25000000>;
> +};
> +
If all are fixed, why do we separate them into three pieces? To show
real internal hardware?

>  &uart0 {
>         status =3D "okay";
>  };
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts=
/sophgo/sg2042.dtsi
> index ead1cc35d88b..e70c43e2ccbe 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -5,6 +5,9 @@
>
>  /dts-v1/;
>  #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/sophgo,sg2042-pll.h>
> +#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
> +#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
>
>  #include "sg2042-cpus.dtsi"
>
> @@ -18,12 +21,54 @@ aliases {
>                 serial0 =3D &uart0;
>         };
>
> +       cgi_main: oscillator0 {
> +               compatible =3D "fixed-clock";
> +               clock-output-names =3D "cgi_main";
> +               #clock-cells =3D <0>;
> +       };
> +
> +       cgi_dpll0: oscillator1 {
> +               compatible =3D "fixed-clock";
> +               clock-output-names =3D "cgi_dpll0";
> +               #clock-cells =3D <0>;
> +       };
> +
> +       cgi_dpll1: oscillator2 {
> +               compatible =3D "fixed-clock";
> +               clock-output-names =3D "cgi_dpll1";
> +               #clock-cells =3D <0>;
> +       };
> +
>         soc: soc {
>                 compatible =3D "simple-bus";
>                 #address-cells =3D <2>;
>                 #size-cells =3D <2>;
>                 ranges;
>
> +               pllclk: clock-controller@70300100c0 {
> +                       compatible =3D "sophgo,sg2042-pll";
> +                       reg =3D <0x70 0x300100c0 0x0 0x40>;
> +                       clocks =3D <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1=
>;
> +                       #clock-cells =3D <1>;
> +               };
> +
> +               rpgate: clock-controller@7030010368 {
> +                       compatible =3D "sophgo,sg2042-rpgate";
> +                       reg =3D <0x70 0x30010368 0x0 0x98>;
> +                       clocks =3D <&clkgen GATE_CLK_RP_CPU_NORMAL>;
> +                       #clock-cells =3D <1>;
> +               };
> +
> +               clkgen: clock-controller@7030012000 {
> +                       compatible =3D "sophgo,sg2042-clkgen";
> +                       reg =3D <0x70 0x30012000 0x0 0x1000>;
> +                       clocks =3D <&pllclk MPLL_CLK>,
> +                                <&pllclk FPLL_CLK>,
> +                                <&pllclk DPLL0_CLK>,
> +                                <&pllclk DPLL1_CLK>;
> +                       #clock-cells =3D <1>;
> +               };
> +
>                 clint_mswi: interrupt-controller@7094000000 {
>                         compatible =3D "sophgo,sg2042-aclint-mswi", "thea=
d,c900-aclint-mswi";
>                         reg =3D <0x00000070 0x94000000 0x00000000 0x00004=
000>;
> @@ -333,6 +378,9 @@ uart0: serial@7040000000 {
>                         interrupt-parent =3D <&intc>;
>                         interrupts =3D <112 IRQ_TYPE_LEVEL_HIGH>;
>                         clock-frequency =3D <500000000>;
> +                       clocks =3D <&clkgen GATE_CLK_UART_500M>,
> +                                <&clkgen GATE_CLK_APB_UART>;
> +                       clock-names =3D "baudclk", "apb_pclk";
>                         reg-shift =3D <2>;
>                         reg-io-width =3D <4>;
>                         status =3D "disabled";
> --
> 2.25.1
>
Others LGTM.

Reviewed-by: Guo Ren <guoren@kernel.org>

--=20
Best Regards
 Guo Ren