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Date: Tue, 20 Feb 2024 09:22:25 +0800
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Subject: Re: [PATCH v10 5/5] riscv: dts: add clock generator for Sophgo SG2042
 SoC
To: Guo Ren <guoren@kernel.org>, Chen Wang <unicornxw@gmail.com>
Cc: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org,
 krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
 palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com,
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 linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
 linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com,
 xiaoguang.xing@sophgo.com, jszhang@kernel.org, inochiama@outlook.com,
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References: <cover.1708223519.git.unicorn_wang@outlook.com>
 <dc899c89e5c30e2267965f185b52d6dded4eb1ac.1708223519.git.unicorn_wang@outlook.com>
 <CAJF2gTRPU6-8Wwds=PRREjU3W0cmCpBcc=w7=J9p_y+XSd3o6w@mail.gmail.com>
From: Chen Wang <unicorn_wang@outlook.com>
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 =?utf-8?B?SE93b25qZnFuNDZTTGRtVzBLY25SZFpnb3dQZFJRb1BkSVY5VWJVVW1JaU1i?=
 =?utf-8?B?MDU3UjJld2lhZEM5UEo4aURXVTJPYkNqZEVBZm13UEo0b0lBN0ZneTQ3Vk9H?=
 =?utf-8?B?bEJHVmszdGQ3K0o1TDlvQ1NQRXZrUGdiYWZtRzN4Y0k5bEI1aDlpWHRyajNE?=
 =?utf-8?B?K3N4WEFSYWFEQjd4c2VEcTkzSkpSME1ZZ3JYbVFCaUxieS9YT1FIZGpkR0h1?=
 =?utf-8?B?OGNWRVVoT3N1MjBnb2pydkJCcGdVME9IdlhMOTZiSUxvL2RNZFFZdVJIdGJp?=
 =?utf-8?B?b3dmU1JUamVUV2F6UTZHYk1IMmtEYUI2bkxVNC9uSXBxSGpiZ2VaQWlFSU82?=
 =?utf-8?B?MkhOUE9FT3EyMlh0TVVyeXkxZFBDTzgvMjJzU29seCt0YVVHVWRuT3ZrTk9M?=
 =?utf-8?B?d2lIUVRpaWZjT0xERHZMYTE5UThjZURLQWVHTzBSZk5YSGErWHFnSThOKzZi?=
 =?utf-8?B?cW1PVFlycHkzWGxnWEhtUTdRQkVCVEJBNE5JZUZLK2tlRXhHUzBZVTkzQ0J4?=
 =?utf-8?B?VlFWQjJlSGQrS2tUUTFXRXRUdFE2Y1FHSnNQcEhaV0hHT3JlL2FRM2d2b3lo?=
 =?utf-8?B?d2ZKWU5GNVJIZ050WVZMWFA5ZWc2VWhoU0s3SzlYS01ZaWZvSzNTZlNXUkx2?=
 =?utf-8?B?RGJ5UXlwcTh5SmY1b3N1ME5PS094dVJoWXJRdlFYRFNMSmxJUkNBVmRiZGNn?=
 =?utf-8?B?c0xXY2lCSUVxS1c2L29VOXFYNjVwbVBuZjA4cEpRYlRxWlFFbjVlSEpPTk1p?=
 =?utf-8?B?VzF4bnIvZXh1KzJnOHVOTVBNOE5wS2VnUklxYnVTbVFHaXd5MGRTNzBpSVFV?=
 =?utf-8?B?TExhdjRtL1ZreFhubTRTbFczZFFuL2g0QnNRTTY5QXJQZWFCckU2L2l2OGEw?=
 =?utf-8?B?S3hIaDAxWVZ4V1FRRDZlZm9DNTcybjByZ1ptc1VrWU5XSWlMYk9QVFJaOS9Q?=
 =?utf-8?B?VzM1MDFROXJ4YTJ5YmNHbkhvYy9PMGFCWm1mVU9ScHZXQ1ZLVUJ0bVVxNGlv?=
 =?utf-8?B?MzZ6N3BJUFBuRTVJVU5qL21ydVl4OTRGaU9CRnQzaVppUmJ6Z1d5cjVQQkNv?=
 =?utf-8?B?Wjd5dHZRcEcycHBzWVh5ekpqRnhNeS9QOVo1TmZ5cW5WSzJtRGFUQW5zQjQ0?=
 =?utf-8?B?Y0swTWYxUlZGMmNUYjArb0kvNmxMSklNdm51dHRFd3VwS0o2WWFSR040Wmg1?=
 =?utf-8?B?OThHN0lpTW1yS0JQR0lUSk5MT0ZtRjY4MVkxT1p2N2YvN2d0S3pObzBleE4z?=
 =?utf-8?B?ckNWdmJ1b2xISFo5RzkvMTJzNXhjY3ltRkwxMnZwUzdRT1JPSnFVSGZWOWg3?=
 =?utf-8?B?S0F4Z2g1cmZjVENtL1J2dktLeVp0R1U0Y0ViTEdvdWdPOXFLMGhkcW9aWUZ1?=
 =?utf-8?B?bzJRWUlTTnVIdWp5UWdxTlFMSkF4ZUYyaCtacFFMTlNxOVVSSVNLSjYzcHdN?=
 =?utf-8?B?VWRTeE54TmtkNDR5Z3liclNiYm02SkYwSm9XYmMvSHo5SkM1U3QzcmVpWHho?=
 =?utf-8?B?TmpTOHlpVVpaMUlFOXd2R3hvVHVRNlVVRFNpbnZKZVRHbjN3czdrR2xPSStk?=
 =?utf-8?Q?yxK+rSOY2I6NrwYtcbtD?=
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On 2024/2/20 9:18, Guo Ren wrote:
> On Sun, Feb 18, 2024 at 10:52 AM Chen Wang <unicornxw@gmail.com> wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add clock generator node to device tree for SG2042, and enable clock for
>> uart.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>> ---
>>   .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  | 12 +++++
>>   arch/riscv/boot/dts/sophgo/sg2042.dtsi        | 48 +++++++++++++++++++
>>   2 files changed, 60 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>> index 49b4b9c2c101..80cb017974d8 100644
>> --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
>> @@ -14,6 +14,18 @@ chosen {
>>          };
>>   };
>>
>> +&cgi_main {
>> +       clock-frequency = <25000000>;
>> +};
>> +
>> +&cgi_dpll0 {
>> +       clock-frequency = <25000000>;
>> +};
>> +
>> +&cgi_dpll1 {
>> +       clock-frequency = <25000000>;
>> +};
>> +
> If all are fixed, why do we separate them into three pieces? To show
> real internal hardware?
Yes, according to TRM, there are three input cgi(Clock Generator IC) on 
board.
>
>>   &uart0 {
>>          status = "okay";
>>   };
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> index ead1cc35d88b..e70c43e2ccbe 100644
>> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> @@ -5,6 +5,9 @@
>>
>>   /dts-v1/;
>>   #include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/clock/sophgo,sg2042-pll.h>
>> +#include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
>> +#include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
>>
>>   #include "sg2042-cpus.dtsi"
>>
>> @@ -18,12 +21,54 @@ aliases {
>>                  serial0 = &uart0;
>>          };
>>
>> +       cgi_main: oscillator0 {
>> +               compatible = "fixed-clock";
>> +               clock-output-names = "cgi_main";
>> +               #clock-cells = <0>;
>> +       };
>> +
>> +       cgi_dpll0: oscillator1 {
>> +               compatible = "fixed-clock";
>> +               clock-output-names = "cgi_dpll0";
>> +               #clock-cells = <0>;
>> +       };
>> +
>> +       cgi_dpll1: oscillator2 {
>> +               compatible = "fixed-clock";
>> +               clock-output-names = "cgi_dpll1";
>> +               #clock-cells = <0>;
>> +       };
>> +
>>          soc: soc {
>>                  compatible = "simple-bus";
>>                  #address-cells = <2>;
>>                  #size-cells = <2>;
>>                  ranges;
>>
>> +               pllclk: clock-controller@70300100c0 {
>> +                       compatible = "sophgo,sg2042-pll";
>> +                       reg = <0x70 0x300100c0 0x0 0x40>;
>> +                       clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
>> +                       #clock-cells = <1>;
>> +               };
>> +
>> +               rpgate: clock-controller@7030010368 {
>> +                       compatible = "sophgo,sg2042-rpgate";
>> +                       reg = <0x70 0x30010368 0x0 0x98>;
>> +                       clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
>> +                       #clock-cells = <1>;
>> +               };
>> +
>> +               clkgen: clock-controller@7030012000 {
>> +                       compatible = "sophgo,sg2042-clkgen";
>> +                       reg = <0x70 0x30012000 0x0 0x1000>;
>> +                       clocks = <&pllclk MPLL_CLK>,
>> +                                <&pllclk FPLL_CLK>,
>> +                                <&pllclk DPLL0_CLK>,
>> +                                <&pllclk DPLL1_CLK>;
>> +                       #clock-cells = <1>;
>> +               };
>> +
>>                  clint_mswi: interrupt-controller@7094000000 {
>>                          compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
>>                          reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
>> @@ -333,6 +378,9 @@ uart0: serial@7040000000 {
>>                          interrupt-parent = <&intc>;
>>                          interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
>>                          clock-frequency = <500000000>;
>> +                       clocks = <&clkgen GATE_CLK_UART_500M>,
>> +                                <&clkgen GATE_CLK_APB_UART>;
>> +                       clock-names = "baudclk", "apb_pclk";
>>                          reg-shift = <2>;
>>                          reg-io-width = <4>;
>>                          status = "disabled";
>> --
>> 2.25.1
>>
> Others LGTM.
>
> Reviewed-by: Guo Ren <guoren@kernel.org>
>