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From: Michael Riesch <michael.riesch@wolfvision.net>
Date: Tue, 20 Feb 2024 10:39:22 +0100
Subject: [PATCH 12/14] media: rockchip: cif: make register access variant
 specific
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To: Mehdi Djait <mehdi.djait.k@gmail.com>, 
 =?utf-8?q?Th=C3=A9o_Lebrun?= <theo.lebrun@bootlin.com>, 
 Thomas Petazzoni <thomas.petazzoni@bootlin.com>, 
 Laurent Pinchart <laurent.pinchart@ideasonboard.com>, 
 Mauro Carvalho Chehab <mchehab@kernel.org>, 
 Rob Herring <robh+dt@kernel.org>, 
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, 
 Conor Dooley <conor+dt@kernel.org>, Heiko Stuebner <heiko@sntech.de>, 
 Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, 
 linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, 
 linux-rockchip@lists.infradead.org, 
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The offsets of the Rockchip CIF registers may differ between the
different variants. Modify the cif_{read,write} methods in order
to support variant specific register offsets

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 drivers/media/platform/rockchip/cif/cif-common.h | 26 ++++++++++++-
 drivers/media/platform/rockchip/cif/cif-dev.c    | 17 +++++++++
 drivers/media/platform/rockchip/cif/cif-regs.h   | 47 ++++++++++--------------
 3 files changed, 61 insertions(+), 29 deletions(-)

diff --git a/drivers/media/platform/rockchip/cif/cif-common.h b/drivers/media/platform/rockchip/cif/cif-common.h
index e5500705eee2..7ecdc820171e 100644
--- a/drivers/media/platform/rockchip/cif/cif-common.h
+++ b/drivers/media/platform/rockchip/cif/cif-common.h
@@ -19,6 +19,8 @@
 #include <media/v4l2-device.h>
 #include <media/videobuf2-v4l2.h>
 
+#include "cif-regs.h"
+
 #define CIF_DRIVER_NAME		"rockchip-cif"
 
 #define CIF_MAX_BUS_CLK		8
@@ -101,6 +103,7 @@ struct cif_match_data {
 	int in_fmts_num;
 	void (*grf_dvp_setup)(struct cif_device *cif_dev);
 	bool has_scaler;
+	unsigned int regs[CIF_REGISTERS_MAX];
 };
 
 struct cif_device {
@@ -121,14 +124,33 @@ struct cif_device {
 	const struct cif_match_data	*match_data;
 };
 
-static inline void cif_write(struct cif_device *cif_dev, unsigned int addr,
+static inline unsigned int cif_get_addr(struct cif_device *cif_device,
+					unsigned int index)
+{
+	if (index >= CIF_REGISTERS_MAX)
+		return CIF_REGISTERS_INVALID;
+
+	return cif_device->match_data->regs[index];
+}
+
+static inline void cif_write(struct cif_device *cif_dev, unsigned int index,
 			     u32 val)
 {
+	unsigned int addr = cif_get_addr(cif_dev, index);
+
+	if (addr == CIF_REGISTERS_INVALID)
+		return;
+
 	writel(val, cif_dev->base_addr + addr);
 }
 
-static inline u32 cif_read(struct cif_device *cif_dev, unsigned int addr)
+static inline u32 cif_read(struct cif_device *cif_dev, unsigned int index)
 {
+	unsigned int addr = cif_get_addr(cif_dev, index);
+
+	if (addr == CIF_REGISTERS_INVALID)
+		return 0;
+
 	return readl(cif_dev->base_addr + addr);
 }
 
diff --git a/drivers/media/platform/rockchip/cif/cif-dev.c b/drivers/media/platform/rockchip/cif/cif-dev.c
index e7b5ae5804ca..929ea39dd832 100644
--- a/drivers/media/platform/rockchip/cif/cif-dev.c
+++ b/drivers/media/platform/rockchip/cif/cif-dev.c
@@ -283,6 +283,23 @@ static const struct cif_match_data px30_cif_match_data = {
 	.in_fmts = px30_in_fmts,
 	.in_fmts_num = ARRAY_SIZE(px30_in_fmts),
 	.has_scaler = true,
+	.regs = {
+		[CIF_CTRL] = 0x00,
+		[CIF_INTEN] = 0x04,
+		[CIF_INTSTAT] = 0x08,
+		[CIF_FOR] = 0x0c,
+		[CIF_LINE_NUM_ADDR] = 0x10,
+		[CIF_FRM0_ADDR_Y] = 0x14,
+		[CIF_FRM0_ADDR_UV] = 0x18,
+		[CIF_FRM1_ADDR_Y] = 0x1c,
+		[CIF_FRM1_ADDR_UV] = 0x20,
+		[CIF_VIR_LINE_WIDTH] = 0x24,
+		[CIF_SET_SIZE] = 0x28,
+		[CIF_SCL_CTRL] = 0x48,
+		[CIF_FRAME_STATUS] = 0x60,
+		[CIF_LAST_LINE] = 0x68,
+		[CIF_LAST_PIX] = 0x6c,
+	},
 };
 
 static const struct of_device_id cif_plat_of_match[] = {
diff --git a/drivers/media/platform/rockchip/cif/cif-regs.h b/drivers/media/platform/rockchip/cif/cif-regs.h
index b8500f0a9ac1..2ce756fde204 100644
--- a/drivers/media/platform/rockchip/cif/cif-regs.h
+++ b/drivers/media/platform/rockchip/cif/cif-regs.h
@@ -9,33 +9,26 @@
 #ifndef _CIF_REGS_H
 #define _CIF_REGS_H
 
-#define CIF_CTRL				0x00
-#define CIF_INTEN				0x04
-#define CIF_INTSTAT				0x08
-#define CIF_FOR					0x0c
-#define CIF_LINE_NUM_ADDR			0x10
-#define CIF_FRM0_ADDR_Y				0x14
-#define CIF_FRM0_ADDR_UV			0x18
-#define CIF_FRM1_ADDR_Y				0x1c
-#define CIF_FRM1_ADDR_UV			0x20
-#define CIF_VIR_LINE_WIDTH			0x24
-#define CIF_SET_SIZE				0x28
-#define CIF_SCM_ADDR_Y				0x2c
-#define CIF_SCM_ADDR_U				0x30
-#define CIF_SCM_ADDR_V				0x34
-#define CIF_WB_UP_FILTER			0x38
-#define CIF_WB_LOW_FILTER			0x3c
-#define CIF_WBC_CNT				0x40
-#define CIF_CROP				0x44
-#define CIF_SCL_CTRL				0x48
-#define CIF_SCL_DST				0x4c
-#define CIF_SCL_FCT				0x50
-#define CIF_SCL_VALID_NUM			0x54
-#define CIF_LINE_LOOP_CTR			0x58
-#define CIF_FRAME_STATUS			0x60
-#define CIF_CUR_DST				0x64
-#define CIF_LAST_LINE				0x68
-#define CIF_LAST_PIX				0x6c
+enum cif_register {
+	CIF_CTRL,
+	CIF_INTEN,
+	CIF_INTSTAT,
+	CIF_FOR,
+	CIF_LINE_NUM_ADDR,
+	CIF_FRM0_ADDR_Y,
+	CIF_FRM0_ADDR_UV,
+	CIF_FRM1_ADDR_Y,
+	CIF_FRM1_ADDR_UV,
+	CIF_VIR_LINE_WIDTH,
+	CIF_SET_SIZE,
+	CIF_SCL_CTRL,
+	CIF_FRAME_STATUS,
+	CIF_LAST_LINE,
+	CIF_LAST_PIX,
+	CIF_REGISTERS_MAX,
+	CIF_REGISTERS_INVALID,
+};
+
 #define CIF_FETCH_Y_LAST_LINE(VAL)		((VAL) & 0x1fff)
 
 #define CIF_CTRL_ENABLE_CAPTURE			BIT(0)

-- 
2.30.2