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From: =?utf-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>, Palmer Dabbelt
 <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Thomas
 Gleixner <tglx@linutronix.de>, Rob Herring <robh+dt@kernel.org>, Krzysztof
 Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Frank Rowand
 <frowand.list@gmail.com>, Conor Dooley <conor+dt@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>, devicetree@vger.kernel.org,
 Saravana Kannan <saravanak@google.com>, Marc Zyngier <maz@kernel.org>,
 Anup Patel <anup@brainfault.org>, linux-kernel@vger.kernel.org, Atish
 Patra <atishp@atishpatra.org>, linux-riscv@lists.infradead.org,
 linux-arm-kernel@lists.infradead.org, Andrew Jones
 <ajones@ventanamicro.com>
Subject: Re: [PATCH v13 07/13] irqchip/riscv-imsic: Add device MSI domain
 support for platform devices
In-Reply-To: <20240220060718.823229-8-apatel@ventanamicro.com>
References: <20240220060718.823229-1-apatel@ventanamicro.com>
 <20240220060718.823229-8-apatel@ventanamicro.com>
Date: Tue, 20 Feb 2024 12:53:05 +0100
Message-ID: <87cysrfj32.fsf@all.your.base.are.belong.to.us>
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Anup Patel <apatel@ventanamicro.com> writes:

> The Linux platform MSI support allows per-device MSI domains so let
> us add a platform irqchip driver for RISC-V IMSIC which provides a
> base IRQ domain with MSI parent support for platform device domains.
>
> This driver assumes that the IMSIC state is already initialized by
> the IMSIC early driver.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  drivers/irqchip/Makefile                   |   2 +-
>  drivers/irqchip/irq-riscv-imsic-platform.c | 346 +++++++++++++++++++++
>  drivers/irqchip/irq-riscv-imsic-state.h    |   1 +
>  3 files changed, 348 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/irqchip/irq-riscv-imsic-platform.c
>
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index d714724387ce..abca445a3229 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -95,7 +95,7 @@ obj-$(CONFIG_QCOM_MPM)			+=3D irq-qcom-mpm.o
>  obj-$(CONFIG_CSKY_MPINTC)		+=3D irq-csky-mpintc.o
>  obj-$(CONFIG_CSKY_APB_INTC)		+=3D irq-csky-apb-intc.o
>  obj-$(CONFIG_RISCV_INTC)		+=3D irq-riscv-intc.o
> -obj-$(CONFIG_RISCV_IMSIC)		+=3D irq-riscv-imsic-state.o irq-riscv-imsic-=
early.o
> +obj-$(CONFIG_RISCV_IMSIC)		+=3D irq-riscv-imsic-state.o irq-riscv-imsic-=
early.o irq-riscv-imsic-platform.o
>  obj-$(CONFIG_SIFIVE_PLIC)		+=3D irq-sifive-plic.o
>  obj-$(CONFIG_IMX_IRQSTEER)		+=3D irq-imx-irqsteer.o
>  obj-$(CONFIG_IMX_INTMUX)		+=3D irq-imx-intmux.o
> diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip=
/irq-riscv-imsic-platform.c
> new file mode 100644
> index 000000000000..7ee44c493dbc
> --- /dev/null
> +++ b/drivers/irqchip/irq-riscv-imsic-platform.c
> @@ -0,0 +1,346 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Western Digital Corporation or its affiliates.
> + * Copyright (C) 2022 Ventana Micro Systems Inc.
> + */
> +
> +#define pr_fmt(fmt) "riscv-imsic: " fmt
> +#include <linux/bitmap.h>
> +#include <linux/cpu.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/module.h>
> +#include <linux/msi.h>
> +#include <linux/platform_device.h>
> +#include <linux/spinlock.h>
> +#include <linux/smp.h>
> +
> +#include "irq-riscv-imsic-state.h"
> +
> +static bool imsic_cpu_page_phys(unsigned int cpu, unsigned int guest_ind=
ex,
> +				phys_addr_t *out_msi_pa)
> +{
> +	struct imsic_global_config *global;
> +	struct imsic_local_config *local;
> +
> +	global =3D &imsic->global;
> +	local =3D per_cpu_ptr(global->local, cpu);
> +
> +	if (BIT(global->guest_index_bits) <=3D guest_index)
> +		return false;
> +
> +	if (out_msi_pa)
> +		*out_msi_pa =3D local->msi_pa +
> +			      (guest_index * IMSIC_MMIO_PAGE_SZ);
> +
> +	return true;
> +}
> +
> +static void imsic_irq_mask(struct irq_data *d)
> +{
> +	imsic_vector_mask(irq_data_get_irq_chip_data(d));
> +}
> +
> +static void imsic_irq_unmask(struct irq_data *d)
> +{
> +	imsic_vector_unmask(irq_data_get_irq_chip_data(d));
> +}
> +
> +static int imsic_irq_retrigger(struct irq_data *d)
> +{
> +	struct imsic_vector *vec =3D irq_data_get_irq_chip_data(d);
> +	struct imsic_local_config *local;
> +
> +	if (WARN_ON(vec =3D=3D NULL))

Checkpatch: use !vec

> +		return -ENOENT;
> +
> +	local =3D per_cpu_ptr(imsic->global.local, vec->cpu);
> +	writel_relaxed(vec->local_id, local->msi_va);
> +	return 0;
> +}
> +
> +static void imsic_irq_compose_vector_msg(struct imsic_vector *vec, struc=
t msi_msg *msg)
> +{
> +	phys_addr_t msi_addr;
> +
> +	if (WARN_ON(vec =3D=3D NULL))

Checkpatch: use !vec

> +		return;
> +
> +	if (WARN_ON(!imsic_cpu_page_phys(vec->cpu, 0, &msi_addr)))
> +		return;
> +
> +	msg->address_hi =3D upper_32_bits(msi_addr);
> +	msg->address_lo =3D lower_32_bits(msi_addr);
> +	msg->data =3D vec->local_id;
> +}
> +
> +static void imsic_irq_compose_msg(struct irq_data *d, struct msi_msg *ms=
g)
> +{
> +	imsic_irq_compose_vector_msg(irq_data_get_irq_chip_data(d), msg);
> +}
> +
> +#ifdef CONFIG_SMP
> +static void imsic_msi_update_msg(struct irq_data *d, struct imsic_vector=
 *vec)
> +{
> +	struct msi_msg msg[2] =3D { [1] =3D { }, };
> +
> +	imsic_irq_compose_vector_msg(vec, msg);
> +	irq_data_get_irq_chip(d)->irq_write_msi_msg(d, msg);
> +}
> +
> +static int imsic_irq_set_affinity(struct irq_data *d, const struct cpuma=
sk *mask_val,
> +				  bool force)
> +{
> +	struct imsic_vector *old_vec, *new_vec;
> +	struct irq_data *pd =3D d->parent_data;
> +
> +	old_vec =3D irq_data_get_irq_chip_data(pd);
> +	if (WARN_ON(old_vec =3D=3D NULL))

Checkpatch: use !old_vec

> +		return -ENOENT;
> +
> +	/* If old vector cpu belongs to the target cpumask then do nothing */
> +	if (cpumask_test_cpu(old_vec->cpu, mask_val))
> +		return IRQ_SET_MASK_OK_DONE;
> +
> +	/* If move is already in-flight then return failure */
> +	if (imsic_vector_get_move(old_vec))
> +		return -EBUSY;
> +
> +	/* Get a new vector on the desired set of CPUs */
> +	new_vec =3D imsic_vector_alloc(old_vec->hwirq, mask_val);
> +	if (!new_vec)
> +		return -ENOSPC;
> +
> +	/* Point device to the new vector */
> +	imsic_msi_update_msg(d, new_vec);
> +
> +	/* Update irq descriptors with the new vector */
> +	pd->chip_data =3D new_vec;
> +
> +	/* Update effective affinity of parent irq data */
> +	irq_data_update_effective_affinity(pd, cpumask_of(new_vec->cpu));
> +
> +	/* Move state of the old vector to the new vector */
> +	imsic_vector_move(old_vec, new_vec);
> +
> +	return IRQ_SET_MASK_OK_DONE;
> +}
> +#endif
> +
> +static struct irq_chip imsic_irq_base_chip =3D {
> +	.name			=3D "IMSIC",
> +	.irq_mask		=3D imsic_irq_mask,
> +	.irq_unmask		=3D imsic_irq_unmask,
> +	.irq_retrigger		=3D imsic_irq_retrigger,
> +	.irq_compose_msi_msg	=3D imsic_irq_compose_msg,
> +	.flags			=3D IRQCHIP_SKIP_SET_WAKE |
> +				  IRQCHIP_MASK_ON_SUSPEND,
> +};
> +
> +static int imsic_irq_domain_alloc(struct irq_domain *domain, unsigned in=
t virq,
> +				  unsigned int nr_irqs, void *args)
> +{
> +	struct imsic_vector *vec;
> +
> +	/* Legacy-MSI or multi-MSI not supported yet. */
> +	if (nr_irqs > 1)
> +		return -ENOTSUPP;

Checkpatch: WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP


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