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Tue, 20 Feb 2024 06:30:49 -0600 Received: from localhost (uda0492258.dhcp.ti.com [172.24.227.9]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 41KCUmfT099249; Tue, 20 Feb 2024 06:30:49 -0600 Date: Tue, 20 Feb 2024 18:00:48 +0530 From: Siddharth Vadapalli To: Manivannan Sadhasivam CC: Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Marek Vasut , Yoshihiro Shimoda , Kishon Vijay Abraham I , Serge Semin , , , , , , Mrinmay Sarkar , Subject: Re: [PATCH v2 4/5] PCI: qcom-ep: Add HDMA support for SA8775P SoC Message-ID: <85374225-287f-4f2a-998b-a1ef997da268@ti.com> References: <20240216-dw-hdma-v2-0-b42329003f43@linaro.org> <20240216-dw-hdma-v2-4-b42329003f43@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20240216-dw-hdma-v2-4-b42329003f43@linaro.org> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 On 24/02/16 11:04PM, Manivannan Sadhasivam wrote: > From: Mrinmay Sarkar > > SA8775P SoC supports the new Hyper DMA (HDMA) DMA Engine inside the DWC IP. > Let's add support for it by passing the mapping format and the number of > read/write channels count. > > The PCIe EP controller used on this SoC is of version 1.34.0, so a separate > config struct is introduced for the sake of enabling HDMA conditionally. > > It should be noted that for the eDMA support (predecessor of HDMA), there > are no mapping format and channels count specified. That is because eDMA > supports auto detection of both parameters, whereas HDMA doesn't. > > Signed-off-by: Mrinmay Sarkar > [mani: Reworded commit message, added kdoc, and minor cleanups] > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Siddharth Vadapalli Regards, Siddharth. > --- > drivers/pci/controller/dwc/pcie-qcom-ep.c | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c > index 45008e054e31..89d06a3e6e06 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c > +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c > @@ -149,6 +149,14 @@ enum qcom_pcie_ep_link_status { > QCOM_PCIE_EP_LINK_DOWN, > }; > > +/** > + * struct qcom_pcie_ep_cfg - Per SoC config struct > + * @hdma_support: HDMA support on this SoC > + */ > +struct qcom_pcie_ep_cfg { > + bool hdma_support; > +}; > + > /** > * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller > * @pci: Designware PCIe controller struct > @@ -803,6 +811,7 @@ static const struct dw_pcie_ep_ops pci_ep_ops = { > > static int qcom_pcie_ep_probe(struct platform_device *pdev) > { > + const struct qcom_pcie_ep_cfg *cfg; > struct device *dev = &pdev->dev; > struct qcom_pcie_ep *pcie_ep; > char *name; > @@ -816,6 +825,14 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) > pcie_ep->pci.ops = &pci_ops; > pcie_ep->pci.ep.ops = &pci_ep_ops; > pcie_ep->pci.edma.nr_irqs = 1; > + > + cfg = of_device_get_match_data(dev); > + if (cfg && cfg->hdma_support) { > + pcie_ep->pci.edma.ll_wr_cnt = 8; > + pcie_ep->pci.edma.ll_rd_cnt = 8; > + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; > + } > + > platform_set_drvdata(pdev, pcie_ep); > > ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); > @@ -874,8 +891,12 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) > qcom_pcie_disable_resources(pcie_ep); > } > > +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { > + .hdma_support = true, > +}; > + > static const struct of_device_id qcom_pcie_ep_match[] = { > - { .compatible = "qcom,sa8775p-pcie-ep", }, > + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, > { .compatible = "qcom,sdx55-pcie-ep", }, > { .compatible = "qcom,sm8450-pcie-ep", }, > { } > > -- > 2.25.1 > >