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bh=IqjOTROjMQYB67bxRQ6W3keFDzFkSXSEKRuI3JlJhrA=; b=eAdzkeVDJnJ2f0NBW01lfF3G/kAuNc4YdScXnuRYSxDAOvtNPKsFnSUqdgz3BtTxqb 6hSsmxFQ/C30jZ0nRTq/ngR8Uk5ECLPrOunYNXeulY3pu0MbV8CdibRXbwZvZ6k2xh5/ N43BRZrJghQfTfbe40V4ndDV4ImgwKy6OhjyIk0ma7uOpRoKXQbPOhQxmg+A8kOVj0nq odrupQJ75jgZBg3sEPdwMj4hOAY3uQZUnQmgo4ToHgMLgUGPPl014oReG/AmFdzvQwid fWfx81LV4IpMlXkQ1iiIP17aLdvtIitQ5HFVatd7rUSWTHX9K7gf4D8CHHNwxEzBV01p lGlw== X-Forwarded-Encrypted: i=1; AJvYcCWMMs1VCuPfV9kQVlw3d3wvFVobwx4R1Z0Zbgd32xKEWpOAsCRQMPCtVC1WWYXp5uZzklclwgL1wdryJ1Ue3NPvkihMjDDRSez/xt2g X-Gm-Message-State: AOJu0YxmuIP9+JbErYObhmaJ3h1+XPXawxIjSjgKlphDEP5DOAZK5a61 FTKz2IOULI2EksApHhgMcYX9ltCbB+TP0LLe7BwoBed7sx4qHCfxYQhet+VqFtaZHZe9GGe6VOk c6JJuJp74A2L1IMe0dgHu1pUsaQ3E4UA4xWhXJQ== X-Received: by 2002:a92:cf0f:0:b0:365:1785:88f6 with SMTP id c15-20020a92cf0f000000b00365178588f6mr10945548ilo.3.1708434959388; Tue, 20 Feb 2024 05:15:59 -0800 (PST) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240220060718.823229-1-apatel@ventanamicro.com> <20240220060718.823229-7-apatel@ventanamicro.com> <87a5nvfj2s.fsf@all.your.base.are.belong.to.us> In-Reply-To: <87a5nvfj2s.fsf@all.your.base.are.belong.to.us> From: Anup Patel Date: Tue, 20 Feb 2024 18:45:47 +0530 Message-ID: Subject: Re: [PATCH v13 06/13] irqchip: Add RISC-V incoming MSI controller early driver To: =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= Cc: Anup Patel , Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley , devicetree@vger.kernel.org, Saravana Kannan , Marc Zyngier , linux-kernel@vger.kernel.org, Atish Patra , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Andrew Jones Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 20, 2024 at 5:23=E2=80=AFPM Bj=C3=B6rn T=C3=B6pel wrote: > > Anup Patel writes: > > > The RISC-V advanced interrupt architecture (AIA) specification > > defines a new MSI controller called incoming message signalled > > interrupt controller (IMSIC) which manages MSI on per-HART (or > > per-CPU) basis. It also supports IPIs as software injected MSIs. > > (For more details refer https://github.com/riscv/riscv-aia) > > > > Let us add an early irqchip driver for RISC-V IMSIC which sets > > up the IMSIC state and provide IPIs. > > > > Signed-off-by: Anup Patel > > This patch has a couple of checkpatch issues: > > CHECK: Alignment should match open parenthesis > CHECK: Please don't use multiple blank lines > CHECK: Please use a blank line after function/struct/union/enum declarati= ons > CHECK: Unnecessary parentheses around 'global->nr_guest_ids < IMSIC_MIN_I= D' > CHECK: Unnecessary parentheses around 'global->nr_guest_ids >=3D IMSIC_MA= X_ID' > CHECK: Unnecessary parentheses around 'global->nr_ids < IMSIC_MIN_ID' > CHECK: Unnecessary parentheses around 'global->nr_ids >=3D IMSIC_MAX_ID' > CHECK: Unnecessary parentheses around global->local > CHECK: Unnecessary parentheses around imsic->lpriv > CHECK: extern prototypes should be avoided in .h files > Okay, I will address these in the next revision. Regards, Anup