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Date: Tue, 20 Feb 2024 15:00:50 +0000
From: Simon Horman <horms@kernel.org>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk,
	davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, xiaoning.wang@nxp.com, wei.fang@nxp.com,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH net] net: phy: realtek: Fix rtl8211f_config_init() for
 RTL8211F(D)(I)-VD-CG PHY
Message-ID: <20240220150050.GO40273@kernel.org>
References: <20240220070007.968762-1-s-vadapalli@ti.com>
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In-Reply-To: <20240220070007.968762-1-s-vadapalli@ti.com>

On Tue, Feb 20, 2024 at 12:30:07PM +0530, Siddharth Vadapalli wrote:
> Commit bb726b753f75 ("net: phy: realtek: add support for
> RTL8211F(D)(I)-VD-CG") extended support of the driver from the existing
> support for RTL8211F(D)(I)-CG PHY to the newer RTL8211F(D)(I)-VD-CG PHY.
> 
> While that commit indicated that the RTL8211F_PHYCR2 register is not
> supported by the "VD-CG" PHY model and therefore updated the corresponding
> section in rtl8211f_config_init() to be invoked conditionally, the call to
> "genphy_soft_reset()" was left as-is, when it should have also been invoked
> conditionally. This is because the call to "genphy_soft_reset()" was first
> introduced by the commit 0a4355c2b7f8 ("net: phy: realtek: add dt property
> to disable CLKOUT clock") since the RTL8211F guide indicates that a PHY
> reset should be issued after setting bits in the PHYCR2 register.
> 
> As the PHYCR2 register is not applicable to the "VD-CG" PHY model, fix the
> rtl8211f_config_init() function by invoking "genphy_soft_reset()"
> conditionally based on the presence of the "PHYCR2" register.
> 
> Fixes: bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Reviewed-by: Simon Horman <horms@kernel.org>