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Date: Tue, 20 Feb 2024 15:13:07 +0000
From: Mark Brown <broonie@kernel.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] arm64/sysreg: Update ID_AA64DFR0_EL1 register
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On Tue, Feb 20, 2024 at 09:18:29AM +0530, Anshuman Khandual wrote:
> This updates ID_AA64DFR0_EL1.PMSVer and ID_AA64DFR0_EL1.DebugVer register
> fields as per the definitions based on DDI0601 2023-12.

Reviewed-by: Mark Brown <broonie@kernel.org>

> @@ -1223,6 +1223,7 @@ UnsignedEnum	35:32	PMSVer
>  	0b0010	V1P1
>  	0b0011	V1P2
>  	0b0100	V1P3
> +	0b0101	V1P4
>  EndEnum

There's also a FEAT_SPE_SME documented in the text but not in the table
of enumerated values (I've reported this) - it makes sense to me to skip
this until the XML is internally consistent.

>  Field	31:28	CTX_CMPs
>  Res0	27:24
> @@ -1249,6 +1250,7 @@ UnsignedEnum	3:0	DebugVer
>  	0b1000	V8P2
>  	0b1001	V8P4
>  	0b1010	V8P8
> +	0b1011	V8P9
>  EndEnum

There's an IMPDEF value defined for this like the 32 bit equivalent but
that was a preexisting issue.

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