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Wed, 21 Feb 2024 02:26:56 +0000 From: Changhuang Liang To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: Ley Foon Tan , Jack Zhu , Changhuang Liang , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 0/2] Add JH8100 external interrupt controller support Date: Tue, 20 Feb 2024 18:26:45 -0800 Message-Id: <20240221022647.5297-1-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: BJSPR01CA0019.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:c::31) To SHXPR01MB0671.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::10) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0671:EE_|SHXPR01MB0541:EE_ X-MS-Office365-Filtering-Correlation-Id: 0b1a4567-c110-4788-fff0-08dc328492f7 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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It can be used to handle high-level input interrupt signals. It also send the output interrupt signal to RISC-V PLIC. changes since v2: - Rebased on tag v6.8-rc4. - Added raw_spinlock_t - Added irq_domain_remove free domain - Updated struct declarations and initializers - Updated variable declarations - Dropped store clk in struct starfive_irq_chip - Replaced "starfive_intc_mod" with "starfive_intc_bit_set&starfive_intc_bit_clear" - Replaced "struct irq_domain *root_domain" with "struct irq_domain *domain" - Added reset_control_assert&clk_disable_unprepare helper functions to error recover v2: https://lore.kernel.org/all/20240130055843.216342-1-changhuang.liang@starfivetech.com/ changes since v1: - Rebased on tag v6.8-rc1. - Dropped store reset_contorl. - Replaced "of_reset_control_get_by_index" with of_reset_control_get_exclusive - Printed the error code via %pe v1: https://lore.kernel.org/all/20240111023201.6187-1-changhuang.liang@starfivetech.com/ Changhuang Liang (2): dt-bindings: interrupt-controller: Add starfive,jh8100-intc irqchip: Add StarFive external interrupt controller .../starfive,jh8100-intc.yaml | 61 +++++ MAINTAINERS | 6 + drivers/irqchip/Kconfig | 11 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-starfive-jh8100-intc.c | 208 ++++++++++++++++++ 5 files changed, 287 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml create mode 100644 drivers/irqchip/irq-starfive-jh8100-intc.c -- 2.25.1