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a=openpgp-sha256; l=1286; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=2Q/c7cqWrxsgCvrUBqcb1kHsDO6XcH9wkH7M5swouBc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBl1XEG3L/MMQLUUU5YiEPeYWXMJ3zBIYu2KPjm4 u+aES6erhyJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZdVxBgAKCRBVnxHm/pHO 9U2QB/kBs6laNU7JRlhgMKm6ASX0OS6MYaQvS2tL1rajvK8SCI69MfZTsB80Q8ODw/yvJz4cMoB NCZN+LPTealKSn8cdF7Jdj2Pw5PVTpMPGZdhNoR3qKAWYYKrHZZ80qVW9yBYfyryS1uiSd/pPRb 8ivwqpEEWugE/H4tUbYYY11Z232YEuuCHE2KlGRUPST1rv3BBp0CAMWfkyACBuX/ked5WvqNa7i EcJt3noB63jTK4wKTeFUEi0ReVpHZhytL7eLBolR+ezbyGIWMFNdiqbu+o7i8+G+ssissRac5w4 9EJmUIOIlinZT7iRQQbWIH/Iu9FVIfulRzxlOiLnanrIXick X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..57a1ea84aa59 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2270,6 +2270,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, dma-coherent; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie0_phy: phy@1c06000 { @@ -2379,6 +2389,16 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; status = "disabled"; + + pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie1_phy: phy@1c0e000 { -- 2.25.1