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References: <20240220060718.823229-1-apatel@ventanamicro.com>
 <20240220060718.823229-11-apatel@ventanamicro.com> <87zfvvgsnr.ffs@tglx>
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From: Anup Patel <apatel@ventanamicro.com>
Date: Wed, 21 Feb 2024 11:12:22 +0530
Message-ID: <CAK9=C2XhUQtYqe2t3HvjxMZw3ffbUCfGfBVrFHf0_Bxtpz-E9g@mail.gmail.com>
Subject: Re: [PATCH v13 10/13] irqchip: Add RISC-V advanced PLIC driver for direct-mode
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Frank Rowand <frowand.list@gmail.com>, 
	Conor Dooley <conor+dt@kernel.org>, Marc Zyngier <maz@kernel.org>, =?UTF-8?B?QmrDtnJuIFTDtnBlbA==?= <bjorn@kernel.org>, 
	Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, 
	Sunil V L <sunilvl@ventanamicro.com>, Saravana Kannan <saravanak@google.com>, 
	Anup Patel <anup@brainfault.org>, linux-riscv@lists.infradead.org, 
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, 
	devicetree@vger.kernel.org
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On Tue, Feb 20, 2024 at 7:10=E2=80=AFPM Thomas Gleixner <tglx@linutronix.de=
> wrote:
>
> On Tue, Feb 20 2024 at 11:37, Anup Patel wrote:
> > +/*
> > + * To handle an APLIC direct interrupts, we just read the CLAIMI regis=
ter
> > + * which will return highest priority pending interrupt and clear the
> > + * pending bit of the interrupt. This process is repeated until CLAIMI
> > + * register return zero value.
> > + */
> > +static void aplic_direct_handle_irq(struct irq_desc *desc)
> > +{
> > +     struct aplic_idc *idc =3D this_cpu_ptr(&aplic_idcs);
> > +     struct irq_domain *irqdomain =3D idc->direct->irqdomain;
> > +     struct irq_chip *chip =3D irq_desc_get_chip(desc);
> > +     irq_hw_number_t hw_irq;
> > +     int irq;
> > +
> > +     chained_irq_enter(chip, desc);
> > +
> > +     while ((hw_irq =3D readl(idc->regs + APLIC_IDC_CLAIMI))) {
> > +             hw_irq =3D hw_irq >> APLIC_IDC_TOPI_ID_SHIFT;
> > +             irq =3D irq_find_mapping(irqdomain, hw_irq);
> > +
> > +             if (unlikely(irq <=3D 0))
> > +                     dev_warn_ratelimited(idc->direct->priv.dev,
> > +                                          "hw_irq %lu mapping not foun=
d\n", hw_irq);
>
> Lacks brackets. See Documentation....

Okay, I will update.

>
> > +             else
> > +                     generic_handle_irq(irq);
> > +     }
> > +
> > +static int aplic_direct_starting_cpu(unsigned int cpu)
> > +{
> > +     if (aplic_direct_parent_irq)
> > +             enable_percpu_irq(aplic_direct_parent_irq,
> > +                               irq_get_trigger_type(aplic_direct_paren=
t_irq));
>
> Ditto.

Okay, I will update.

>
> > +     return 0;
> > +}
>
> > +void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode)
> > +{
> > +     u32 val;
> > +#ifdef CONFIG_RISCV_M_MODE
> > +     u32 valH;
>
> No camel case please.

Okay.

>
> > +
> > +     if (msi_mode) {
> > +             val =3D lower_32_bits(priv->msicfg.base_ppn);
> > +             valH =3D FIELD_PREP(APLIC_xMSICFGADDRH_BAPPN, upper_32_bi=
ts(priv->msicfg.base_ppn));
> > +             valH |=3D FIELD_PREP(APLIC_xMSICFGADDRH_LHXW, priv->msicf=
g.lhxw);
> > +             valH |=3D FIELD_PREP(APLIC_xMSICFGADDRH_HHXW, priv->msicf=
g.hhxw);
> > +             valH |=3D FIELD_PREP(APLIC_xMSICFGADDRH_LHXS, priv->msicf=
g.lhxs);
> > +             valH |=3D FIELD_PREP(APLIC_xMSICFGADDRH_HHXS, priv->msicf=
g.hhxs);
> > +             writel(val, priv->regs + APLIC_xMSICFGADDR);
> > +             writel(valH, priv->regs + APLIC_xMSICFGADDRH);
> > +     }
>
> Thanks,
>
>         tglx

Regards,
Anup