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Subject: Re: [PATCH v8 1/4] kvm: arm64: introduce new flag for non-cacheable
 IO memory
Thread-Topic: [PATCH v8 1/4] kvm: arm64: introduce new flag for non-cacheable
 IO memory
Thread-Index: AQHaY86h4Cva4mNx7U65b8+zrBQke7ETSjgAgAEELEw=
Date: Wed, 21 Feb 2024 06:01:10 +0000
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References: <20240220072926.6466-1-ankita@nvidia.com>
 <20240220072926.6466-2-ankita@nvidia.com> <ZdS2yl1kzZv/h+vH@lpieralisi>
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=0A=
>> Lastly, adapt the stage2 PTE property setter function=0A=
>> (stage2_set_prot_attr) to handle the NormalNC attribute.=0A=
>>=0A=
>> [1] section D8.5.5 - DDI0487J_a_a-profile_architecture_reference_manual.=
pdf=0A=
>> [2] section B2.8 - DDI0487J_a_a-profile_architecture_reference_manual.pd=
f=0A=
>> [3] sections 1.7.7.3/1.8.5.2/appendix C - DEN0029H_SBSA_7.1.pdf=0A=
>>=0A=
>=0A=
> A couple of Link: tags would not hurt in my opinion, lest we forget:=0A=
>=0A=
> Link: https://lore.kernel.org/r/20230907181459.18145-2-ankita@nvidia.com/=
=0A=
> Link: https://lore.kernel.org/r/20231205033015.10044-1-ankita@nvidia.com=
=0A=
=0A=
Agreed, will add.=