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Subject: Re: [PATCH 1/7] drivers/perf: hisi_pcie: Introduce
 hisi_pcie_pmu_get_filter()
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
References: <20240204074527.47110-1-yangyicong@huawei.com>
 <20240204074527.47110-2-yangyicong@huawei.com>
 <20240208120643.000042fa@Huawei.com> <20240208121800.000057a2@huawei.com>
From: Yicong Yang <yangyicong@huawei.com>
Message-ID: <68d4382d-7b1a-f23e-3b33-c2fca708deaf@huawei.com>
Date: Wed, 21 Feb 2024 17:39:11 +0800
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On 2024/2/8 20:18, Jonathan Cameron wrote:
> On Thu, 8 Feb 2024 12:06:43 +0000
> Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:
> 
>> On Sun, 4 Feb 2024 15:45:21 +0800
>> Yicong Yang <yangyicong@huawei.com> wrote:
>>
>>> From: Yicong Yang <yangyicong@hisilicon.com>
>>>
>>> Factor out retrieving of the register value for the
>>> corresponding event from hisi_pcie_config_filter() into a
>>> new function hisi_pcie_pmu_get_filter() allowing future reuse.
>>>
>>> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>  
>>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> On second thoughts, this might benefit from a clearer name.
> Perhaps just call it exactly what it is
> hisi_pcie_pmu_get_ctrl_reg_val_to_set()
> 
> It incorporates the event code as well as the filter.
> Maybe we want to rename pmu_config_filter() as well to
> pmu_config_counter() which I think is the real meaning?
> 

make sense to me. we can simply use the reg name as the suffix,
it'll be more clearer:

hisi_pcie_pmu_get_event_ctrl_val()
hisi_pcie_pmu_config_event_ctrl()

> 
>>
>>> ---
>>>  drivers/perf/hisilicon/hisi_pcie_pmu.c | 13 ++++++++++---
>>>  1 file changed, 10 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c
>>> index b90ba8aca3fa..11a819cd07f2 100644
>>> --- a/drivers/perf/hisilicon/hisi_pcie_pmu.c
>>> +++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c
>>> @@ -216,10 +216,8 @@ static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset,
>>>  	writeq_relaxed(val, pcie_pmu->base + offset);
>>>  }
>>>  
>>> -static void hisi_pcie_pmu_config_filter(struct perf_event *event)
>>> +static u64 hisi_pcie_pmu_get_filter(struct perf_event *event)
>>>  {
>>> -	struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
>>> -	struct hw_perf_event *hwc = &event->hw;
>>>  	u64 port, trig_len, thr_len, len_mode;
>>>  	u64 reg = HISI_PCIE_INIT_SET;
>>>  
>>> @@ -256,6 +254,15 @@ static void hisi_pcie_pmu_config_filter(struct perf_event *event)
>>>  	else
>>>  		reg |= FIELD_PREP(HISI_PCIE_LEN_M, HISI_PCIE_LEN_M_DEFAULT);
>>>  
>>> +	return reg;
>>> +}
>>> +
>>> +static void hisi_pcie_pmu_config_filter(struct perf_event *event)
>>> +{
>>> +	struct hisi_pcie_pmu *pcie_pmu = to_pcie_pmu(event->pmu);
>>> +	struct hw_perf_event *hwc = &event->hw;
>>> +	u64 reg = hisi_pcie_pmu_get_filter(event);
>>> +
>>>  	hisi_pcie_pmu_writeq(pcie_pmu, HISI_PCIE_EVENT_CTRL, hwc->idx, reg);
>>>  }
>>>    
>>
>>
>> _______________________________________________
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> 
> .
>