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Date: Wed, 21 Feb 2024 10:57:58 +0000
From: Sakari Ailus <sakari.ailus@iki.fi>
To: Mehdi Djait <mehdi.djait.k@gmail.com>
Cc: mchehab@kernel.org, heiko@sntech.de, hverkuil-cisco@xs4all.nl,
	krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org,
	conor+dt@kernel.org, linux-media@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	thomas.petazzoni@bootlin.com, alexandre.belloni@bootlin.com,
	maxime.chevallier@bootlin.com, paul.kocialkowski@bootlin.com,
	michael.riesch@wolfvision.net, laurent.pinchart@ideasonboard.com,
	Mehdi Djait <mehdi.djait@bootlin.com>,
	Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [RESEND Patch v13 1/3] media: dt-bindings: media: add bindings
 for Rockchip CIF
Message-ID: <ZdXXNvGl-2CZdnhk@valkosipuli.retiisi.eu>
References: <cover.1707677804.git.mehdi.djait.k@gmail.com>
 <13deb8c5cb58e08c1b47decd112b51e8e0b6c4dc.1707677804.git.mehdi.djait.k@gmail.com>
 <Zcta6hhSio67ahKs@valkosipuli.retiisi.eu>
 <ZdTbilKCsMFcjz64@mehdi-archlinux>
 <ZdT97Szv3yYG9Xbb@valkosipuli.retiisi.eu>
 <ZdUQBl5pkFg2i1iu@mehdi-archlinux>
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In-Reply-To: <ZdUQBl5pkFg2i1iu@mehdi-archlinux>

Hi Mehdi,

On Tue, Feb 20, 2024 at 09:48:06PM +0100, Mehdi Djait wrote:
> Hi Sakari,
> 
> On Tue, Feb 20, 2024 at 07:30:53PM +0000, Sakari Ailus wrote:
> > Hi Mehdi,
> > 
> > On Tue, Feb 20, 2024 at 06:04:10PM +0100, Mehdi Djait wrote:
> > > Hi Sakari,
> > > 
> > > Thank you for the review.
> > 
> > You're welcome!
> > 
> > > 
> > > On Tue, Feb 13, 2024 at 12:04:58PM +0000, Sakari Ailus wrote:
> > > > Hi Mehdi,
> > > > 
> > > > Thanks for the patchset.
> > > > 
> > > > On Sun, Feb 11, 2024 at 08:03:30PM +0100, Mehdi Djait wrote:
> > > > > From: Mehdi Djait <mehdi.djait@bootlin.com>
> > > > > 
> > > > > Add a documentation for the Rockchip Camera Interface binding.
> > > > > 
> > > > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
> > > > > Signed-off-by: Mehdi Djait <mehdi.djait@bootlin.com>
> > > > > Signed-off-by: Mehdi Djait <mehdi.djait.k@gmail.com>
> > > > > ---
> > > > >  .../bindings/media/rockchip,px30-vip.yaml     | 123 ++++++++++++++++++
> > > > >  1 file changed, 123 insertions(+)
> > > > >  create mode 100644 Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > > > 
> > > > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..6af4a9b6774a
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > > > @@ -0,0 +1,123 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > > > +%YAML 1.2
> > > > > +---
> > > > > +$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml#
> > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > +
> > > > > +title: Rockchip Camera Interface (CIF)
> > > > > +
> > > > > +maintainers:
> > > > > +  - Mehdi Djait <mehdi.djait@bootlin.com>
> > > > > +
> > > > > +description:
> > > > > +  CIF is a camera interface present on some Rockchip SoCs. It receives the data
> > > > > +  from Camera sensor or CCIR656 encoder and transfers it into system main memory
> > > > > +  by AXI bus.
> > > > > +
> > > > > +properties:
> > > > > +  compatible:
> > > > > +    const: rockchip,px30-vip
> > > > > +
> > > > > +  reg:
> > > > > +    maxItems: 1
> > > > > +
> > > > > +  interrupts:
> > > > > +    maxItems: 1
> > > > > +
> > > > > +  clocks:
> > > > > +    items:
> > > > > +      - description: ACLK
> > > > > +      - description: HCLK
> > > > > +      - description: PCLK
> > > > > +
> > > > > +  clock-names:
> > > > > +    items:
> > > > > +      - const: aclk
> > > > > +      - const: hclk
> > > > > +      - const: pclk
> > > > > +
> > > > > +  resets:
> > > > > +    items:
> > > > > +      - description: AXI
> > > > > +      - description: AHB
> > > > > +      - description: PCLK IN
> > > > > +
> > > > > +  reset-names:
> > > > > +    items:
> > > > > +      - const: axi
> > > > > +      - const: ahb
> > > > > +      - const: pclkin
> > > > > +
> > > > > +  power-domains:
> > > > > +    maxItems: 1
> > > > > +
> > > > > +  ports:
> > > > > +    $ref: /schemas/graph.yaml#/properties/ports
> > > > > +
> > > > > +    properties:
> > > > > +      port@0:
> > > > > +        $ref: /schemas/graph.yaml#/$defs/port-base
> > > > > +        unevaluatedProperties: false
> > > > > +        description: input port on the parallel interface
> > > > > +
> > > > > +        properties:
> > > > > +          endpoint:
> > > > > +            $ref: video-interfaces.yaml#
> > > > > +            unevaluatedProperties: false
> > > > > +
> > > > > +            properties:
> > > > > +              bus-type:
> > > > > +                enum: [5, 6]
> > > > > +
> > > > > +            required:
> > > > > +              - bus-type
> > > > 
> > > > What about the vsync-active, hsync-active and data-active properties?
> > > > Aren't they relevant for this device? Are there default values? This should
> > > > be part of the bindings for the device, shouldn't it?
> > > > 
> > > 
> > > From what I gathered from the Rockchip PX30 TRM and the other
> > > available documents from Rockchip, I will add the following:
> > > 
> > > diff --git a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > index 6af4a9b6774a..6920b0cb0507 100644
> > > --- a/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > +++ b/Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
> > > @@ -69,6 +69,14 @@ properties:
> > >                bus-type:
> > >                  enum: [5, 6]
> > >  
> > > +              hsync-active:
> > > +                enum: [0, 1]
> > > +                default: 1
> > > +
> > > +              vsync-active:
> > > +                enum: [0, 1]
> > > +                default: 0
> > 
> > I'd use the same default for both, whether it's 0 or 1.
> > 
> 
> Is this supposed to be the default value HIGH or LOW if it is not
> configured by the driver ? because the manual states the following:
> 
> HREF_POL
> Href input polarity:
> 1'b0 : high active
> 1'b1 : low active
> RESET VALUE: 0x0
> 
> VSYNC_POL
> Vsync input polarity:
> 1'b0 : low active
> 1'b1 : high active
> RESET VALUE: 0x0
> 
> And that's why I chose 1 for hsync and 0 for vsync

The hardware reset values do not have to reflect defaults in DT bindings.

-- 
Kind regards,

Sakari Ailus