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Wed, 21 Feb 2024 05:35:37 -0800 (PST) Message-ID: <1a3c9ec5-69b9-4f55-bdf6-628fcf2b0268@tuxon.dev> Date: Wed, 21 Feb 2024 15:35:35 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 10/17] clk: renesas: r9a08g045: Add support for power domains Content-Language: en-US To: Geert Uytterhoeven Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Claudiu Beznea References: <20240208124300.2740313-1-claudiu.beznea.uj@bp.renesas.com> <20240208124300.2740313-11-claudiu.beznea.uj@bp.renesas.com> From: claudiu beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi, Geert, On 16.02.2024 16:10, Geert Uytterhoeven wrote: > Hi Claudiu, > > On Thu, Feb 8, 2024 at 1:44 PM Claudiu wrote: >> From: Claudiu Beznea >> >> Instantiate power domains for the currently enabled IPs of R9A08G045 SoC. >> >> Signed-off-by: Claudiu Beznea > > Thanks for your patch! > >> --- a/drivers/clk/renesas/r9a08g045-cpg.c >> +++ b/drivers/clk/renesas/r9a08g045-cpg.c >> @@ -240,6 +240,28 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = { >> MOD_CLK_BASE + R9A08G045_DMAC_ACLK, >> }; >> >> +static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = { >> + DEF_PD("always-on", R9A08G045_PD_ALWAYS_ON, 0, 0, >> + RZG2L_PD_F_PARENT | RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("gic", R9A08G045_PD_GIC, MSTOP(ACPU, BIT(3)), PWRDN(IP1, 2), > > My docs document only bit 0 of the CPG_BUS_ACPU_MSTOP register. Indeed, mine, too. I took as reference the table "Registers for Module Standby Mode". I asked for clarifications. The TF-A software also uses BIT(3) for setting this. > >> + RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("ia55", R9A08G045_PD_IA55, MSTOP(PERI_CPU, BIT(13)), PWRDN(IP1, 3), >> + RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("dmac", R9A08G045_PD_DMAC, MSTOP(REG1, GENMASK(3, 0)), 0, >> + RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("ddr", R9A08G045_PD_DDR, MSTOP(PERI_DDR, BIT(1)), PWRDN(IP2, 0), > > Only BIT(1)? My docs suggest GENMASK(1, 0). I wanted to keep PHY separated but there's no reason for doing that, AFAICT. I'll update it. > >> + RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("tzcddr", R9A08G045_PD_TZCDDR, MSTOP(TZCDDR, GENMASK(2, 0)), >> + PWRDN(IP2, 1), RZG2L_PD_F_ALWAYS_ON), >> + DEF_PD("otfde_ddr", R9A08G045_PD_OTFDE_DDR, 0, PWRDN(IP2, 2), RZG2L_PD_F_ALWAYS_ON), > > MSTOP(PERI_CPU2, BIT(2))? OK. Thank you, Claudiu Beznea > >> + DEF_PD("sdhi0", R9A08G045_PD_SDHI0, MSTOP(PERI_COM, BIT(0)), PWRDN(IP1, 13), 0), >> + DEF_PD("sdhi1", R9A08G045_PD_SDHI1, MSTOP(PERI_COM, BIT(1)), PWRDN(IP1, 14), 0), >> + DEF_PD("sdhi2", R9A08G045_PD_SDHI2, MSTOP(PERI_COM, BIT(11)), PWRDN(IP1, 15), 0), >> + DEF_PD("eth0", R9A08G045_PD_ETHER0, MSTOP(PERI_COM, BIT(2)), PWRDN(IP1, 11), 0), >> + DEF_PD("eth1", R9A08G045_PD_ETHER1, MSTOP(PERI_COM, BIT(3)), PWRDN(IP1, 12), 0), >> + DEF_PD("scif0", R9A08G045_PD_SCIF0, MSTOP(MCPU2, BIT(1)), 0, 0), >> +}; >> + > > The rest LGTM. > > Gr{oetje,eeting}s, > > Geert > > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds