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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id f2-20020a05620a280200b00785c9ab3067si11974153qkp.117.2024.02.21.06.06.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Feb 2024 06:06:43 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-74852-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; arc=fail (body hash mismatch); spf=pass (google.com: domain of linux-kernel+bounces-74852-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-74852-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 869D81C23569 for ; Wed, 21 Feb 2024 14:06:43 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 90F9C7E57B; Wed, 21 Feb 2024 14:05:34 +0000 (UTC) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 93CDF7C6C0; Wed, 21 Feb 2024 14:05:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708524334; cv=none; b=WIJg51dYPqH9uVDQKoEGyt+jsP0ev53STWB3SnB8FvgXUgx+jV29y0SkIrGi9d+uddR+5xPT8Zrhw7dREakO7/oNu8q1j8EuEaAqSxlkTIN+z4WW6tVSSlcRr0vCnWDqVVyyid1jCKtero0b52Xx4IK3ZzGV7AwLtM0iKoyc0iQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708524334; c=relaxed/simple; bh=fa5UFx328+uy1ItN2onmayxTMv1ZPciMAR0Fx3yRX1A=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=R/kRNHE7/rfrMqYL1aKjklvR2p9UlPkdz8BX3WV5c6R4X8UR8gg1MNenRyF+R9aVIaHIDguETJe2ajhxarhRxkLuGQK17dRVUt/0IOtnH7Nl2aN6rDPaZ9IJrFiRdXxvLW5mS6tmRxYiY4hhVhRv2T2yvR7ZMw/bT7/d3Uok7qc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD55DFEC; Wed, 21 Feb 2024 06:06:08 -0800 (PST) Received: from FVFF77S0Q05N (unknown [10.57.65.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BE97C3F762; Wed, 21 Feb 2024 06:05:27 -0800 (PST) Date: Wed, 21 Feb 2024 14:05:24 +0000 From: Mark Rutland To: Mark Brown Cc: Anshuman Khandual , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, will@kernel.org, catalin.marinas@arm.com, James Clark , Rob Herring , Marc Zyngier , Suzuki Poulose , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , linux-perf-users@vger.kernel.org Subject: Re: [PATCH V16 1/8] arm64/sysreg: Add BRBE registers and fields Message-ID: References: <20240125094119.2542332-1-anshuman.khandual@arm.com> <20240125094119.2542332-2-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Feb 21, 2024 at 01:59:03PM +0000, Mark Brown wrote: > On Wed, Feb 21, 2024 at 01:52:38PM +0000, Mark Rutland wrote: > > On Thu, Jan 25, 2024 at 03:11:12PM +0530, Anshuman Khandual wrote: > > > Minor nit, but could we please list thse in order: > > > BRBCR_EL1 > > BRBCR_EL12 > > BRBCR_EL2 > > > ... since that way the names are ordered alphnumerically, which is what we've > > done for other groups (e.g. PIR_EL{1,12,2}), and it's the way the ARM ARM > > happens to be ordered. > > It's a good point about the sorting, though the file is currently mostly > sorted by encoding rather than alphanumerically (similarly to how > sysreg.h was done). Sure, we're inconsistent. I'd just prefer that there's *some* local ordering here, as the patch is neither ordered as above nor by encoding: Sysreg BRBCR_EL2 2 4 9 0 0 .. Sysreg BRBCR_EL1 2 1 9 0 0 .. Sysreg BRBCR_EL12 2 5 9 0 0 Mark.