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Date: Thu, 22 Feb 2024 08:28:00 +0800
From: Inochi Amaoto <inochiama@outlook.com>
To: Chen Wang <unicornxw@gmail.com>
Cc: aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, 
	krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, 
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	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, 
	xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, 
	Chen Wang <unicorn_wang@outlook.com>
Subject: Re: [PATCH v3 3/4] riscv: dts: add reset generator for Sophgo SG2042
 SoC
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LGTM

Reviewed-by: Inochi Amaoto <inochiama@outlook.com>

On Tue, Jan 30, 2024 at 09:50:32AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Add reset generator node to device tree for SG2042.
> 
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index ead1cc35d88b..eeb341e16bfd 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -6,6 +6,8 @@
>  /dts-v1/;
>  #include <dt-bindings/interrupt-controller/irq.h>
>  
> +#include <dt-bindings/reset/sophgo,sg2042-reset.h>
> +
>  #include "sg2042-cpus.dtsi"
>  
>  / {
> @@ -327,6 +329,12 @@ intc: interrupt-controller@7090000000 {
>  			riscv,ndev = <224>;
>  		};
>  
> +		rstgen: reset-controller@7030013000 {
> +			compatible = "sophgo,sg2042-reset";
> +			reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
> +			#reset-cells = <1>;
> +		};
> +
>  		uart0: serial@7040000000 {
>  			compatible = "snps,dw-apb-uart";
>  			reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
> -- 
> 2.25.1
>