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Date: Thu, 22 Feb 2024 08:35:14 +0800
From: Inochi Amaoto <inochiama@outlook.com>
To: Chen Wang <unicornxw@gmail.com>, aou@eecs.berkeley.edu, 
	chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, 
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	robh+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, 
	linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, 
	guoren@kernel.org, jszhang@kernel.org
Cc: Chen Wang <unicorn_wang@outlook.com>, 
	Inochi Amaoto <inochiama@outlook.com>
Subject: Re: [PATCH v3 4/4] riscv: dts: add resets property for uart node
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LGTM

Reviewed-by: Inochi Amaoto <inochiama@outlook.com>

On Tue, Jan 30, 2024 at 09:50:51AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
> 
> Add resets property for uart0 for completeness, although it is
> deasserted by default.
> 
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index eeb341e16bfd..81fda312f988 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -343,6 +343,7 @@ uart0: serial@7040000000 {
>  			clock-frequency = <500000000>;
>  			reg-shift = <2>;
>  			reg-io-width = <4>;
> +			resets = <&rstgen RST_UART0>;
>  			status = "disabled";
>  		};
>  	};
> -- 
> 2.25.1
>