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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="lHpyoJFoRpJTBuEw" Content-Disposition: inline In-Reply-To: <20240222035158.195265-1-dharma.b@microchip.com> --lHpyoJFoRpJTBuEw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > diff --git a/Documentation/devicetree/bindings/interrupt-controller/atmel= ,aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/atmel,ai= c.yaml > new file mode 100644 > index 000000000000..0d51bd78bf2b > --- /dev/null > +++ b/Documentation/devicetree/bindings/interrupt-controller/atmel,aic.ya= ml > @@ -0,0 +1,89 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/interrupt-controller/atmel,aic.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Advanced Interrupt Controller (AIC) > + > +maintainers: > + - Nicolas Ferre > + - Dharma balasubiramani > + > +description: > + The Advanced Interrupt Controller (AIC) is an 8-level priority, indivi= dually > + maskable, vectored interrupt controller providing handling of up to one > + hundred and twenty-eight interrupt sources. > + > +allOf: > + - $ref: /schemas/interrupt-controller.yaml# > + - if: > + properties: > + compatible: > + contains: > + const: atmel,at91rm9200-aic > + then: > + properties: > + atmel,external-irqs: > + minItems: 1 > + maxItems: 7 > + else: > + properties: > + atmel,external-irqs: > + minItems: 1 > + maxItems: 1 When there's property restrictions being applied, move the allof down to... > + > +properties: > + compatible: > + enum: > + - atmel,at91rm9200-aic > + - atmel,sama5d2-aic > + - atmel,sama5d3-aic > + - atmel,sama5d4-aic > + - microchip,sam9x60-aic > + > + reg: > + maxItems: 1 > + > + interrupt-controller: true > + > + "#interrupt-cells": > + const: 3 > + description: | > + The 1st cell is the IRQ number (Peripheral IDentifier on datasheet= ). > + The 2nd cell specifies flags: > + bits[3:0] trigger type and level flags: > + 1 =3D low-to-high edge triggered. > + 2 =3D high-to-low edge triggered. > + 4 =3D active high level-sensitive. > + 8 =3D active low level-sensitive. > + Valid combinations: 1, 2, 3, 4, 8. > + Default for internal sources: 4 (active high). > + The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest). > + > + interrupts: > + maxItems: 1 > + > + atmel,external-irqs: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: u32 array of external irqs. =2E..here. Both work, but seeing the restrictions before you see any of the properties is not the most understandable. Cheers, Conor. > +required: > + - compatible > + - reg > + - interrupt-controller > + - "#interrupt-cells" > + - atmel,external-irqs > + > +unevaluatedProperties: false > + > +examples: > + - | > + interrupt-controller@fffff000 { > + compatible =3D "atmel,at91rm9200-aic"; > + reg =3D <0xfffff000 0x200>; > + interrupt-controller; > + #interrupt-cells =3D <3>; > + atmel,external-irqs =3D <31>; > + }; > +... >=20 > base-commit: 4f5e5092fdbf5cec6bedc19fbe69cce4f5f08372 > --=20 > 2.25.1 >=20 --lHpyoJFoRpJTBuEw Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCZdcMLQAKCRB4tDGHoIJi 0iOsAP9m+bcNCJqOinLb0AteBdy7mXRGcB1XbQsicq2MgSjpjQD+MssNTCXfQ6vt gzfH0TbEBfWso1aovIY/r1JDSDcpoA8= =wd3E -----END PGP SIGNATURE----- --lHpyoJFoRpJTBuEw--