Received: by 2002:a05:7412:798b:b0:fc:a2b0:25d7 with SMTP id fb11csp230973rdb; Thu, 22 Feb 2024 01:44:34 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCW9GRNumjF5xyViVo38WrrQHKd5llINR28pdNR/gb4Wer8Q111l9W04EuMXRZD6YaqWLsGWJ/xQ2R2EqDvReWIizbZD7ztGbm/nqm75SA== X-Google-Smtp-Source: AGHT+IEOmD3aeNAZz6qx5I6RQH99OcAn0BMn6p8Nk9YUdflmzmJCKekKTYLOBnlkt/HWfRHfBZZS X-Received: by 2002:a17:903:8c3:b0:1db:a52a:ccb7 with SMTP id lk3-20020a17090308c300b001dba52accb7mr23848892plb.1.1708595074011; Thu, 22 Feb 2024 01:44:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1708595073; cv=pass; d=google.com; s=arc-20160816; b=PJMmMo/mBMAKPBWJbtC/ZyM+PMixE2/vTjgSIntgqyVk7rUzYwPXH3ogju7VSfQ41g FBtlHrSwEmu24BPlP8mIW6pSgKV7c1jO/fvg/YgrEV0/GD4sCiqmQuTcQVuIsYE/XTQx C7Zr+aUEv/nnJkBgbbta9tG9KWWwL1INatapZhpwXtik88SJYzA2dnQm9t2OFQi1qv18 mIq+waE4tBFH50vkZvMFukdW1mm2ch5VfC0e2QZj0ukf1IXeJ/19lTsLfJeS0QTxy4o9 U0aWW8mkIHs51cMfaVRx3lUyXAOYB3AKRh5qN/0IyqsNYuEROxfU4Jd/Ruch0ViOQGNM 97uA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jp730QJfPl3UdF1ypk+MZODRkE+rBOU76pBYGEsA07M=; fh=wlH51IodtzN34EX/mXVpAgo5hrogl12L55xwL59u/oo=; b=jme2GZ7ChwRNpiSgzVMT/or0aOX6n/IZQbW1n/wjSThpCBrAigkJHbn9sF4rjkFlu7 N2M2PmiesSqHSVj0H8aCOTycakeKeF/KYAdpI/EG8+O6/+TS1eK6B9kIVt3l6V0T8ltU tEFTmQGFOb1KFsg0GwiDJ9bP8tERboWCZTkx6nwQjKd1B47WyfbpsHcJDQaPAfNxGUtk RZ3FFp/BF+uNU9BRv+O2UHcAmNB/evTsqlQ4MQLUIMW0oV3nyCF59BiI8IvOAZJ2/ZvJ C8obj8TzkKzzShCDgneo35wfWkQBOpvbJjcVpbAgyniucl0//yxtvTIH2PxfYPRWZE3Z de1Q==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NFcAwanV; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-76252-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-76252-linux.lists.archive=gmail.com@vger.kernel.org" Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id mb3-20020a170903098300b001dbedc935ecsi7645340plb.241.2024.02.22.01.44.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 01:44:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-76252-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NFcAwanV; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-76252-linux.lists.archive=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-76252-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 4D6FF286AFF for ; Thu, 22 Feb 2024 09:44:00 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7042C39861; Thu, 22 Feb 2024 09:42:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="NFcAwanV" Received: from mail-oi1-f176.google.com (mail-oi1-f176.google.com [209.85.167.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F4041740 for ; Thu, 22 Feb 2024 09:42:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708594923; cv=none; b=lsBsH5AG/Ro7n5NYx7omv50xvGxsQDD/VSH32y6w7huQsJnTLWc6JtKXqSJvrEgh7s8d3MVhuGiKw6xqdmMpRk5nTdYTkj5tl+JHLji+buNskOquOeXHKpXXjCUY4YI+u83VCsp7vGP2P39HbhUyZ7rzC3WYVpow2SI+mPBntWk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708594923; c=relaxed/simple; bh=Jq677SKEM38g+jVBPgtBStA3mG/f0yhqJeCpfC43444=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nevaDFtacOwI1A1HbSHFTAMx1xXj0GakB/0ZxWOXblZ0Tq8ryAK9bOv/RAVEXNW49PZCRXRncUIaD8ObPr4hgi5ylArD0ziRbO7CjgYUIVtXz1QAnWE2kWiEJhFhW1nVCKiQiQl1nYow/bx4sDm5+b1r+YnCYD4Sm0pL7zQMkv4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=NFcAwanV; arc=none smtp.client-ip=209.85.167.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-oi1-f176.google.com with SMTP id 5614622812f47-3bbc649c275so886710b6e.0 for ; Thu, 22 Feb 2024 01:42:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1708594921; x=1709199721; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jp730QJfPl3UdF1ypk+MZODRkE+rBOU76pBYGEsA07M=; b=NFcAwanVdKMVs3nU5BCxVeQJXw6m+Vxul+lah+Ogbie/SNPcCxrlRr5n2idMh/ET6z cSg4MlR3jkAmwcuhZKQXgT14PhPgW/brCSFJpVaUBZJjN+szIDXJLxtb6Su8QTPFJaq6 g0nfMU+1YSYooc7Q9Jy0OT5fj7AnGyjCb0HrCG5mf2ZQpS1UqOSnAr6733PFQwr1FaY2 56cp5LyTqzfAw7ei5vcdqe0p5UJaEmvlkV3xsNB96XDWHPC5EeGrzwkg6FEwM/Fpgs4u jyuCC01XWd6np050FM5pYNDj2hBUqnk2bgJH0+KZinKzD7ppWzDiL4SGtYZHj1xMabDd 6sPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1708594921; x=1709199721; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jp730QJfPl3UdF1ypk+MZODRkE+rBOU76pBYGEsA07M=; b=s+1yhPYKJmNnEZOgULhXN+X5KZmdqBnTTRl6ZSdS7Me4V+uq+wrtS/k5+vyA/ADf4N qCaXOZt0nYjHIn0yiyxSN/7ZAM0jFHTLGoGLK+l2mZXGfpeVUkw4TyZFd4Fls4YYhxBf oBav85rrTE9h1T7x4XdjjNQsEM7oPjytyjhewmWD0lGmu+IEGNVy0p8nDrdY2UhltCZq EZ2pcJ0i0xHzAqqjMBjUMKC1fqVX5HGG6xUPDrdMUxVoOSiHMK4miC9sYA0vEIYkY1qf zWilj9ypqGSq/kFyFoy/MYBrnlXKAT/TzHtq6VJURdhrdhrdVPSRK5PYpiT5atAL1kA4 NAfg== X-Forwarded-Encrypted: i=1; AJvYcCU8uROCgRrdczu4iNUrrXyCHyR4yBcmosBHX8iUTC1K5VHTG/srTz1rDTAtpshtyTDEQtfMVDlxXIdyVFaYYWpFW/D/mg33liHcJRpm X-Gm-Message-State: AOJu0Yzb2xncLoEU+vXNM7u4UB305bxQ3a9HKGtskfAoTpOjg7CRbi/R 2oVtkXYAY6KvPQXvQ2xjgxGj5S2xybXmPesJBZc6/54teQG9zpOWZq3Lp9hMv7Y= X-Received: by 2002:a05:6808:308a:b0:3c1:782e:b8e1 with SMTP id bl10-20020a056808308a00b003c1782eb8e1mr1966233oib.39.1708594920963; Thu, 22 Feb 2024 01:42:00 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id n15-20020a05680803af00b003c17c2b8d09sm130699oie.31.2024.02.22.01.41.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Feb 2024 01:42:00 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Frank Rowand , Conor Dooley Cc: Marc Zyngier , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Atish Patra , Andrew Jones , Sunil V L , Saravana Kannan , Anup Patel , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Anup Patel Subject: [PATCH v14 13/18] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Date: Thu, 22 Feb 2024 15:10:01 +0530 Message-Id: <20240222094006.1030709-14-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240222094006.1030709-1-apatel@ventanamicro.com> References: <20240222094006.1030709-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Linux PCI framework supports per-device MSI domains for PCI devices so extend the IMSIC driver to allow PCI per-device MSI domains. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++++ drivers/irqchip/irq-riscv-imsic-platform.c | 35 ++++++++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 85f86e31c996..2fc0cb32341a 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -553,6 +553,13 @@ config RISCV_IMSIC select GENERIC_IRQ_MATRIX_ALLOCATOR select GENERIC_MSI_IRQ +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index e2344fc08dca..90ddcdd0bba5 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -208,6 +209,28 @@ static const struct irq_domain_ops imsic_base_domain_ops = { #endif }; +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + irq_chip_unmask_parent(d); + pci_msi_unmask_irq(d); +} + +#define MATCH_PCI_MSI BIT(DOMAIN_BUS_PCI_MSI) + +#else + +#define MATCH_PCI_MSI 0 + +#endif + static bool imsic_init_dev_msi_info(struct device *dev, struct irq_domain *domain, struct irq_domain *real_parent, @@ -231,6 +254,13 @@ static bool imsic_init_dev_msi_info(struct device *dev, /* Is the target supported? */ switch (info->bus_token) { +#ifdef CONFIG_RISCV_IMSIC_PCI + case DOMAIN_BUS_PCI_DEVICE_MSI: + case DOMAIN_BUS_PCI_DEVICE_MSIX: + info->chip->irq_mask = imsic_pci_mask_irq; + info->chip->irq_unmask = imsic_pci_unmask_irq; + break; +#endif case DOMAIN_BUS_DEVICE_MSI: /* * Per-device MSI should never have any MSI feature bits @@ -270,11 +300,12 @@ static bool imsic_init_dev_msi_info(struct device *dev, #define MATCH_PLATFORM_MSI BIT(DOMAIN_BUS_PLATFORM_MSI) static const struct msi_parent_ops imsic_msi_parent_ops = { - .supported_flags = MSI_GENERIC_FLAGS_MASK, + .supported_flags = MSI_GENERIC_FLAGS_MASK | + MSI_FLAG_PCI_MSIX, .required_flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS, .bus_select_token = DOMAIN_BUS_NEXUS, - .bus_select_mask = MATCH_PLATFORM_MSI, + .bus_select_mask = MATCH_PCI_MSI | MATCH_PLATFORM_MSI, .init_dev_msi_info = imsic_init_dev_msi_info, }; -- 2.34.1