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bh=SUuCGHBfr+e9wXEmhb8mV4moLDcmcxBNTGHyspNshv4=; b=bN9vPhX5RQymB4F+Z9mwZMpt3PpHyWTh3eFFHXIpR2vzqansK3HVahdU KPosKJsl8bnPrzoSa4HbalO+pK0RpLBLIMV6mAoG1PnJpmgsHGVy10rN+ /sBZ4UT2bCwuxXg4dHDHFKwynyHkxAUs2mapH3JbmG6crVNz4AxV8zc9c Uk63pRLbO6qv071RSP9j+ZuO6V5NAHz9Qu9geVikT+rQVXkDWNOj7qHJX 6msGTCIaerZA+ChJtqBz2G7wK+G8ioej3+Z2dhVcm9yel2u98iQ0LdUaY UmmYO8wQONRq2y0R44m01kT0V7PQL8Vfc+8xdTbpQYNH08RaH0qRroaq+ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10992"; a="5801777" X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="5801777" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2024 08:01:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="36363798" Received: from ijarvine-desk1.ger.corp.intel.com (HELO localhost) ([10.94.249.55]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2024 08:01:39 -0800 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 22 Feb 2024 18:01:34 +0200 (EET) To: Rengarajan S cc: kumaravel.thiagarajan@microchip.com, tharunkumar.pasumarthi@microchip.com, gregkh@linuxfoundation.org, jirislaby@kernel.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, unglinuxdriver@microchip.com Subject: Re: [PATCH v1 tty] 8250: microchip: pci1xxxx: Refactor TX Burst code to use pre-existing APIs In-Reply-To: <20240222134944.1131952-1-rengarajan.s@microchip.com> Message-ID: <37490c91-a48f-e0a1-ec92-2307c08260e2@linux.intel.com> References: <20240222134944.1131952-1-rengarajan.s@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Thu, 22 Feb 2024, Rengarajan S wrote: > Updated the TX Burst implementation by changing the circular buffer > processing with the pre-existing APIs in kernel. Also updated conditional > statements and alignment issues for better readability. > > Signed-off-by: Rengarajan S > --- > @@ -434,16 +435,7 @@ static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) > > xmit = &port->state->xmit; > > - if (port->x_char) { > - writeb(port->x_char, port->membase + UART_TX); > - port->icount.tx++; > - port->x_char = 0; > - return; > - } > - > - if ((uart_tx_stopped(port)) || (uart_circ_empty(xmit))) { > - port->ops->stop_tx(port); > - } else { > + if (!(port->x_char)) { > data_empty_count = (pci1xxxx_read_burst_status(port) & > UART_BST_STAT_TX_COUNT_MASK) >> 8; > do { > @@ -453,15 +445,22 @@ static void pci1xxxx_tx_burst(struct uart_port *port, u32 uart_status) > &data_empty_count, > &valid_byte_count); > > - port->icount.tx++; > if (uart_circ_empty(xmit)) > break; > } while (data_empty_count && valid_byte_count); > + } else { > + writeb(port->x_char, port->membase + UART_TX); > + port->icount.tx++; > + port->x_char = 0; > + return; Why you made this reorganization for x_char handling?? It seems entirely wrong thing to do, x_char should have precendence over sending normal chars. This patch would have been some much simpler to review if it would have not attempted to n things in one go, please try to split into sensible changes. -- i.