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Date: Thu, 22 Feb 2024 10:12:13 -0800 (PST)
Subject:     Re: [PATCH v6 0/4] StarFive's StarLink PMU Support
In-Reply-To: <20240222125707.GA8589@willie-the-truck>
CC: jisheng.teoh@starfivetech.com, corbet@lwn.net,
  Mark Rutland <mark.rutland@arm.com>, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
  dan.j.williams@intel.com, ilkka@os.amperecomputing.com, Jonathan.Cameron@huawei.com,
  dave.jiang@intel.com, leyfoon.tan@starfivetech.com, linux-doc@vger.kernel.org,
  linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
From: Palmer Dabbelt <palmer@dabbelt.com>
To: Will Deacon <will@kernel.org>
Message-ID: <mhng-008f9a14-40fe-4522-93f1-e7ebb1233931@palmer-ri-x1c9a>
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On Thu, 22 Feb 2024 04:57:08 PST (-0800), Will Deacon wrote:
> On Mon, Jan 29, 2024 at 05:51:37PM +0800, Ji Sheng Teoh wrote:
>> This patch series adds support for StarFive's Starlink Performance
>> Monitor Unit(PMU).
>> StarFive's StarLink PMU integrates one or more CPU cores with
>> a shared L3 memory system. The PMU supports overflow interrupt,
>> up to 16 programmable 64bit event counters, and an independent
>> 64bit cycle counter.
>> StarLink PMU is accessed via MMIO.
>>
>> Example Perf stat output:
>> [root@user]# perf stat -a -e /starfive_starlink_pmu/cycles/ \
>>         -e /starfive_starlink_pmu/read_miss/ \
>>         -e /starfive_starlink_pmu/read_hit/ \
>>         -e /starfive_starlink_pmu/release_request/  \
>>         -e /starfive_starlink_pmu/write_hit/ \
>>         -e /starfive_starlink_pmu/write_miss/ \
>>         -e /starfive_starlink_pmu/write_request/ \
>>         -e /starfive_starlink_pmu/writeback/ \
>>         -e /starfive_starlink_pmu/read_request/ \
>>         -- openssl speed rsa2048
>> Doing 2048 bits private rsa's for 10s: 5 2048 bits private RSA's in
>> 2.84s
>> Doing 2048 bits public rsa's for 10s: 169 2048 bits public RSA's in
>> 2.42s
>> version: 3.0.11
>> built on: Tue Sep 19 13:02:31 2023 UTC
>> options: bn(64,64)
>> CPUINFO: N/A
>>                   sign    verify    sign/s verify/s
>> rsa 2048 bits 0.568000s 0.014320s      1.8     69.8
>> /////////
>>  Performance counter stats for 'system wide':
>>
>>          649991998      starfive_starlink_pmu/cycles/
>>            1009690      starfive_starlink_pmu/read_miss/
>>            1079750      starfive_starlink_pmu/read_hit/
>>            2089405      starfive_starlink_pmu/release_request/
>>                129      starfive_starlink_pmu/write_hit/
>>                 70      starfive_starlink_pmu/write_miss/
>>                194      starfive_starlink_pmu/write_request/
>>             150080      starfive_starlink_pmu/writeback/
>>            2089423      starfive_starlink_pmu/read_request/
>>
>>       27.062755678 seconds time elapsed
>>
>> Ji Sheng Teoh (4):
>>   perf: starfive: Add StarLink PMU support
>>   dt-bindings: perf: starfive: Add JH8100 StarLink PMU
>>   docs: perf: Add description for StarFive's StarLink PMU
>>   MAINTAINERS: Add entry for StarFive StarLink PMU
>>
>>  Documentation/admin-guide/perf/index.rst      |   1 +
>>  .../perf/starfive_starlink_pmu.rst            |  46 ++
>>  .../perf/starfive,jh8100-starlink-pmu.yaml    |  46 ++
>>  MAINTAINERS                                   |   7 +
>>  drivers/perf/Kconfig                          |   9 +
>>  drivers/perf/Makefile                         |   1 +
>>  drivers/perf/starfive_starlink_pmu.c          | 643 ++++++++++++++++++
>>  7 files changed, 753 insertions(+)
>>  create mode 100644 Documentation/admin-guide/perf/starfive_starlink_pmu.rst
>>  create mode 100644 Documentation/devicetree/bindings/perf/starfive,jh8100-starlink-pmu.yaml
>>  create mode 100644 drivers/perf/starfive_starlink_pmu.c
>
> Palmer, are you ok with me taking this via the perf tree? I usually
> leave the Risc-V stuff for you, but this one doesn't touch the arch code
> at all.

Sorry I missed these

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>

> Cheers,
>
> Will