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bh=iujBheYzPS2kiDl/x9jHkvTLileZkPYaz+fw9bZi8/k=; b=TPyR72Wlm1ztz1MMcTYXAFOV64jE8LQbzyTYyqJ+ZgZDPUbLAeSM1sIW XUhBewP1pvoh/nGIeT2udEkW03A5lWhrr+KX4Ak+zKGHd/xOFa7IOtfXO rI9zOA4msc7n7E28SHT3i5C5oSeAjJxV8QIZgPTTttX7pb1+WdaB8Py7d ZmF49raZTuCBA9Fm9oKDYn+xGRKZdk1CAcNmM+/jNLn41w5vQ4W6M9bX8 X87zh2TILkuvCNGn5amm7hIsbW39VQ6GFA5M+hzU3ETnTskMBJIiWS47b RGYjrjXIAppIAUOAvq4PeZc6NOWajYxdbmdU70SBT2PnJ5maf9TwqKmNE A==; X-IronPort-AV: E=McAfee;i="6600,9927,10992"; a="3020535" X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="3020535" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2024 10:50:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10992"; a="936889164" X-IronPort-AV: E=Sophos;i="6.06,179,1705392000"; d="scan'208";a="936889164" Received: from agluck-desk3.sc.intel.com ([172.25.222.74]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2024 10:50:45 -0800 From: Tony Luck To: "Chatre, Reinette" , Borislav Petkov , James Morse Cc: Thomas Gleixner , x86@kernel.org, linux-kernel@vger.kernel.org, "Yu, Fenghua" , Ingo Molnar , H Peter Anvin , Babu Moger , shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Tony Luck Subject: [PATCH v3 0/2] x86/resctrl: Pass domain to target CPU Date: Thu, 22 Feb 2024 10:50:37 -0800 Message-ID: <20240222185039.72201-1-tony.luck@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When a function is called via IPI, it isn't possible for assertions in source code to check that the right locks are held when those locks were obtained by the sender of the IPI. Restructure some code to avoid the need for the check. Patch 1 has the actual fix Patch 2 is just some code cleanups Changes since V2: 1) Rebased on TIP x86/cache 2) Added a missed setting of msr_param.dom in resctrl_arch_update_one() 3) Dropped the code that used separate msr_param structures for CDP 4) Added lockdep_assert_cpus_held() to get_domain_from_cpu() 5) Split into two patches Tony Luck (2): x86/resctrl: Pass domain to target CPU x86/resctrl: Simply call convention for MSR update functions arch/x86/kernel/cpu/resctrl/internal.h | 4 +- arch/x86/kernel/cpu/resctrl/core.c | 55 +++++++++-------------- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 42 +++++------------ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 14 ++---- 4 files changed, 37 insertions(+), 78 deletions(-) base-commit: c0d848fcb09d80a5f48b99f85e448185125ef59f -- 2.43.0