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a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1708637638; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=PrJ6YaFxatvY2iijd5Wqk9LxjgKfLoik+dqgECHQvCc=; b=E8IKGWFobvMuydi/MYlCGtioOqkIyOjB766pK5NO0O5XAbWMgtCQk2EakY7kz56uIkMp3A fJbScBQ7wtn6rKFXSCse7HAP0zIHNNRFq8Ui3HnKIRcHVv/O9A7dOQ6zsE4xtAO/3shZDu 23y7JebnE1ZqgWTCB3f+GBIYWpf2KD4JcGH/n7wROMMpEU5bjsYRQQkyvREUxOWN/82puZ yudaq144aPD64IIrSwauXD1UAtqhEMgF3BHJg+rFhOCmk9oLQQttGgkoVbUWVsWI1tTVVf mqGzlP45wJkqZqOGx/jyqNSr6gyeRP5Z+KfnumjcBO+2r6ws4mpxbJxuDmtoag== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1708637638; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=PrJ6YaFxatvY2iijd5Wqk9LxjgKfLoik+dqgECHQvCc=; b=fDIU63ciUTcRIKaxF7jIPyC9HLb4PBqsycE7avUV7D+2/qWfEpyl+pqC54WNOiNeW+0k7b moIvBy70qNb/RwAw== To: Yu Chien Peter Lin , acme@kernel.org, adrian.hunter@intel.com, ajones@ventanamicro.com, alexander.shishkin@linux.intel.com, andre.przywara@arm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atishp@atishpatra.org, conor+dt@kernel.org, conor.dooley@microchip.com, conor@kernel.org, devicetree@vger.kernel.org, evan@rivosinc.com, geert+renesas@glider.be, guoren@kernel.org, heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, locus84@andestech.com, magnus.damm@gmail.com, mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com, namhyung@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, peterlin@andestech.com, peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, sunilvl@ventanamicro.com, tim609@andestech.com, uwu@icenowy.me, wens@csie.org, will@kernel.org, inochiama@outlook.com, unicorn_wang@outlook.com, wefu@redhat.com Cc: Randolph , Atish Patra Subject: Re: [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number In-Reply-To: <20240222083946.3977135-3-peterlin@andestech.com> References: <20240222083946.3977135-1-peterlin@andestech.com> <20240222083946.3977135-3-peterlin@andestech.com> Date: Thu, 22 Feb 2024 22:33:58 +0100 Message-ID: <87r0h4dvzt.ffs@tglx> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain On Thu, Feb 22 2024 at 16:39, Yu Chien Peter Lin wrote: > Currently, the implementation of the RISC-V INTC driver uses the > interrupt cause as the hardware interrupt number, with a maximum of > 64 interrupts. However, the platform can expand the interrupt number > further for custom local interrupts. > > To fully utilize the available local interrupt sources, switch > to using irq_domain_create_tree() that creates the radix tree > map, add global variables (riscv_intc_nr_irqs, riscv_intc_custom_base > and riscv_intc_custom_nr_irqs) to determine the valid range of local > interrupt number (hwirq). > > Signed-off-by: Yu Chien Peter Lin > Reviewed-by: Randolph > Reviewed-by: Anup Patel > Reviewed-by: Atish Patra Reviewed-by: Thomas Gleixner