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Date: Fri, 23 Feb 2024 07:24:24 +0800
User-Agent: Mozilla Thunderbird
Subject: Re: [PATCH RFC 3/4] dt-binding: clock: merge all hisilicon clock
 bindings to hisilicon,clock-reset-generator
To: Rob Herring <robh@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>,
 Stephen Boyd <sboyd@kernel.org>,
 Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
 Conor Dooley <conor+dt@kernel.org>, David Yang <mmyangfl@gmail.com>,
 linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org
References: <20240216-clk-mv200-v1-0-a29ace29e636@outlook.com>
 <20240216-clk-mv200-v1-3-a29ace29e636@outlook.com>
 <20240222201411.GA3765548-robh@kernel.org>
Content-Language: en-US
From: Yang Xiwen <forbidden405@outlook.com>
In-Reply-To: <20240222201411.GA3765548-robh@kernel.org>
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 =?utf-8?B?MHE1R2VSZ28wMXFvYThHNDVpb25Ta1QzM2dSZmJ1VCtBV2hVa1dtWnN1U0hG?=
 =?utf-8?B?Y0JPNkNveFQ0WEJGL3lkL2h3dXgxWjRyMlU3N2x6YUVQUTVWU1kwZFhSbWVx?=
 =?utf-8?B?TFc4TW0rZWxsNlZ5UjNPYUVzOXBtT21WbzZPKy96YTg5SEFYeHdKazZIa0pC?=
 =?utf-8?B?RUtnM0dITjcyK0dOUU8xV1JlRkk0UHBaMmx5QUh6UmRhaDFOWW9ObERNeXEy?=
 =?utf-8?B?d2VMK3QzSGlURW5XaGRFZkUyMFFkYVBIOUFHeFZ0UlUzN3V1dUQwMkpUVE9y?=
 =?utf-8?B?L1hKdCtPMXQ1Y3pjc3JESGVoZnJuVzJUeDlyUG5jdFRvQzlOSGdaMVMvZ3A5?=
 =?utf-8?B?MWVFc2I0Smx5QmhIZFA2b2FCN2JVZGlvdXVvbFQvYW5SejlQcG5XME9DWEZt?=
 =?utf-8?B?dXlrdlgzcTBJZ3ZaZ2NsNDJjVE93eVpISURkVk5WME5CZC9xR29IRGxubXlP?=
 =?utf-8?B?RUU0NkNhSWNudVQ0bDNnTUZ1bWl2VXlqVmY1THNuWFE2TkxrSGg0NGkwOUFv?=
 =?utf-8?B?VFprYTB5N0YxT0paU0tIY2RSVWYrU3VxaldhWUd6SHdEVnVPaHY0NTk5cWN4?=
 =?utf-8?B?OTNUOFJTaTNUK2tReHA2Umh1YjBaazExdDlWbFlIMGU2NVM3SzNiV051d1dN?=
 =?utf-8?B?RXlhcnlEZlRwaWVCeFc2S1RWaXZ4L1UvNDk0Q1VSUVhyVVZUVmxYMi9MRmVy?=
 =?utf-8?B?MFcyZG5Yc0hseWdtQlFoSGZzZmRrM0NKTnh2Ulhmc0pUYmVIaWdzVERlYVph?=
 =?utf-8?B?ZUtDNEo1R2orYjFBVDVJelZCdXhVdVBxM01wczZYN1oxbyt6Q1RVRUtkR01m?=
 =?utf-8?B?anBhd1ZHeGhLV0lEdlEveEZ0UFAwcFo1VVBnaGVvcmxhRmEzMUt5VjNyZ0U3?=
 =?utf-8?B?MkNvWURpTCtSMkcwWnhpZWFJOVJaOVdFeFIzdC8rRlVNM0ZwbkY5Tyt1OUQ4?=
 =?utf-8?B?N0tmdUxyTnpNZmJZWE1ERW0yVDNwekYxVThyM2pQMVBNL2dheVJ6MUduZWdL?=
 =?utf-8?B?eWRtLzNHa3BTRzBsMFduU0xWREtleWZNU1JQcWYxYUhnbWpEWnA4enlmcXpN?=
 =?utf-8?B?eXlnNWFGeThxak96WjBzaXFUWFBzREJONFdhSm5SS1A5TXlLY3hWR0VxdlEy?=
 =?utf-8?B?Yno2MTlIald1Rmw1a3cxQ3d3NU9hcWI1ZUVQZVFFb0pCc3dldnUxWmxzcE5p?=
 =?utf-8?B?ZFFhUElGTXk4Yit6N3E1L2JYKzFsV2h6YUM5a2pCSytTT2JqVnNVVnlLQUwx?=
 =?utf-8?B?czFVYm81SzJ6Zm0vbFpmWWlNaU9YdXFRb2wxd28wNzNZZDNqb2VjQWNoMzA4?=
 =?utf-8?B?ZUR6eWhRL1I0aDgyMUsrVTBybzliMzZrKzlWUEFYWEFoL0lQM3JGdEUzRlJa?=
 =?utf-8?B?NkJtd1MxNlg4cGh2dmdaWnAwS1ZBd0JsMFVOZ3J4ZHIveE92bWZLQk5jOXBw?=
 =?utf-8?B?d21IUDVjTFZzVHlRRE0rSmxza0RITVNlb2l5WXhEbUV6cGhtRmxWNUVmbkov?=
 =?utf-8?B?UmtiTEdPdGpoSHI3c2ZWUlNRZXdJeGFIaEs4ZEowSG8reGFDNHIvdDVUNEtU?=
 =?utf-8?B?b1hJWmpJSGRpbWJleTlCT3FXenpjRUNOSDR1Yk9mazBrR2xZaUx1TEFzQ3Bm?=
 =?utf-8?B?Y01IOXFWRWxnZVhhV0NMalU4MjlCNUVNMUlHa0dXWXM3NzJ3bURtM1ZuU1Bt?=
 =?utf-8?Q?bZv71sfjthLx7Xci6+bVV+HtTUrt9xMgFRconJS?=
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On 2/23/2024 4:14 AM, Rob Herring wrote:
> On Fri, Feb 16, 2024 at 07:37:53PM +0800, Yang Xiwen wrote:
>> We don't need so many separated and duplicated dt-binding files. Merge
>> them all and convert them to YAML.
>>
>> Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
>> ---
>>   .../devicetree/bindings/clock/hi3660-clock.txt     |  47 -------
>>   .../devicetree/bindings/clock/hi3670-clock.txt     |  43 -------
>>   .../devicetree/bindings/clock/hi6220-clock.txt     |  52 --------
>>   .../devicetree/bindings/clock/hisi-crg.txt         |  50 --------
>>   .../clock/hisilicon,clock-reset-generator.yaml     | 139 +++++++++++++++++++++
>>   .../clock/hisilicon,hi3559av100-clock.yaml         |  59 ---------
>>   6 files changed, 139 insertions(+), 251 deletions(-)
>
>> diff --git a/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
>> new file mode 100644
>> index 000000000000..d37cd892473e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/hisilicon,clock-reset-generator.yaml
>> @@ -0,0 +1,139 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/hisilicon,clock-reset-generator.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Hisilicon SOC Clock and Reset Generator (CRG) module
>> +
>> +maintainers:
>> +  - Yang Xiwen <forbidden405@foxmail.com>
>> +
>> +description: |
> Don't need '|' if no formatting. Here and elsewhere.
>
>> +  Hisilicon SOC clock control module which supports the clocks, resets and
>> +  power domains on various SoCs.
>> +
>> +properties:
>> +  compatible:
>> +    minItems: 1
>> +    items:
>> +      - enum:
>> +          - hisilicon,hi3559av100-clock
>> +          - hisilicon,hi3559av100-shub-clock
>> +          - hisilicon,hi3660-crgctrl
>> +          - hisilicon,hi3660-pctrl
>> +          - hisilicon,hi3660-pmuctrl
>> +          - hisilicon,hi3660-sctrl
>> +          - hisilicon,hi3660-iomcu
>> +          - hisilicon,hi3660-stub-clk
>> +          - hisilicon,hi3670-crgctrl
>> +          - hisilicon,hi3670-pctrl
>> +          - hisilicon,hi3670-pmuctrl
>> +          - hisilicon,hi3670-sctrl
>> +          - hisilicon,hi3670-iomcu
>> +          - hisilicon,hi3670-media1-crg
>> +          - hisilicon,hi3670-media2-crg
>> +          - hisilicon,hi6220-acpu-sctrl
>> +          - hisilicon,hi6220-aoctrl
>> +          - hisilicon,hi6220-sysctrl
>> +          - hisilicon,hi6220-mediactrl
>> +          - hisilicon,hi6220-pmctrl
>> +          - hisilicon,hi6220-stub-clk
>> +          - hisilicon,hi3516cv300-crg
>> +          - hisilicon,hi3516cv300-sysctrl
>> +          - hisilicon,hi3519-crg
>> +          - hisilicon,hi3798cv200-crg
>> +          - hisilicon,hi3798cv200-sysctrl
>> +      - const: syscon
>> +      - const: simple-mfd
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  '#reset-cells':
>> +    enum: [1, 2]
>> +    description: |
>> +      First cell is reset request register offset.
>> +      Second cell is bit offset in reset request register.
>> +
>> +  '#address-cells':
>> +    const: 1
>> +
>> +  '#size-cells':
>> +    const: 1
>> +
>> +  mboxes:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> Standard property already has a type. You need to define how many
> entries and what each one is if more than 1.
>
>> +    description: |
>> +      Phandle to the mailbox for sending msg to MCU
>> +      (See ../mailbox/hisilicon,hi3660-mailbox.txt for more info)
> Convert or avoid adding new references to txt bindings.
>
>> +
>> +  mbox-names:
>> +    $ref: /schemas/types.yaml#/definitions/string-array
>> +    description: |
>> +      Names of the mailboxes.
>> +
>> +  hisilicon,hi6220-clk-sram:
>> +    $ref: /schemas/types.yaml#/definitions/phandle
>> +    description: |
>> +      Phandle to the syscon managing the SoC internal sram
>> +      the driver needs using the sram to pass parameters for frequency change.
>> +
>> +  reset-controller:
>> +    type: object
>> +    description: |
>> +      Reset controller for Hi3798CV200 GMAC module
>> +
>> +required:
>> +  - compatible
>> +  - '#clock-cells'
>> +
>> +allOf:
>> +  - if:
>> +      properties:
>> +        compatible:
>> +          not:
>> +            contains:
>> +              enum:
>> +                - hisilicon,hi3798cv200-crg
>> +    then:
>> +      properties:
>> +        reset-controller: false
>> +  - oneOf:
>> +      - required:
>> +          - hisilicon,hi6220-clk-sram
>> +      - required:
>> +          - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/hi3559av100-clock.h>
>> +    soc {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        clock-controller@12010000 {
>> +            compatible = "hisilicon,hi3559av100-clock";
>> +            #clock-cells = <1>;
>> +            #reset-cells = <2>;
>> +            reg = <0x0 0x12010000 0x0 0x10000>;
>> +        };
>> +    };
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    #include <dt-bindings/clock/hi3660-clock.h>
>> +    soc {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        clock-controller@fff35000 {
>> +            compatible = "hisilicon,hi3660-crgctrl", "syscon";
>> +            reg = <0x0 0xfff35000 0x0 0x1000>;
>> +            #clock-cells = <1>;
>> +        };
>> +    };


Never mind. I've decided to leave them as-is. Now I'm focusing on 
hisi-crg.txt only. (We've already at RFC v4,   this patch set is outdated)

-- 
Regards,
Yang Xiwen