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Date: Fri, 23 Feb 2024 10:18:52 +0100
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: William Zhang <william.zhang@broadcom.com>
Cc: Linux MTD List <linux-mtd@lists.infradead.org>, Linux ARM List
 <linux-arm-kernel@lists.infradead.org>, Broadcom Kernel List
 <bcm-kernel-feedback-list@broadcom.com>, f.fainelli@gmail.com,
 kursad.oney@broadcom.com, joel.peshkin@broadcom.com,
 anand.gore@broadcom.com, dregan@mail.com, kamal.dasu@broadcom.com,
 tomer.yacoby@broadcom.com, dan.beygelman@broadcom.com, David Regan
 <dregan@broadcom.com>, linux-kernel@vger.kernel.org, Vignesh Raghavendra
 <vigneshr@ti.com>, Brian Norris <computersforpeace@gmail.com>, Richard
 Weinberger <richard@nod.at>
Subject: Re: [PATCH v6 12/13] mtd: rawnand: brcmnand: Add support for
 getting ecc setting from strap
Message-ID: <20240223101852.005da3ad@xps-13>
In-Reply-To: <20240223034758.13753-13-william.zhang@broadcom.com>
References: <20240223034758.13753-1-william.zhang@broadcom.com>
	<20240223034758.13753-13-william.zhang@broadcom.com>
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Hi William,

william.zhang@broadcom.com wrote on Thu, 22 Feb 2024 19:47:57 -0800:

> BCMBCA broadband SoC based board design does not specify ecc setting in
> dts but rather use the SoC NAND strap info to obtain the ecc strength
> and spare area size setting. Add brcm,nand-ecc-use-strap dts propety for
> this purpose and update driver to support this option. However these two
> options can not be used at the same time.
>=20
> Signed-off-by: William Zhang <william.zhang@broadcom.com>
> Reviewed-by: David Regan <dregan@broadcom.com>
>=20

FYI I did not receive patches 7, 8, 9, which makes the series numbering
very odd.

> ---
>=20
> Changes in v6:
> - Combine the ecc step size and ecc strength into one get function
> - Treat it as error condition if both brcm,nand-ecc-use-strap and nand
> ecc dts properties are set
> - Add intermediate steps to get the sector size bitfield
>=20
> Changes in v5: None
> Changes in v4:
> - Update the comments for ecc setting selection
>=20
> Changes in v3: None
> Changes in v2:
> - Minor cosmetic fixes
>=20
>  drivers/mtd/nand/raw/brcmnand/brcmnand.c | 83 ++++++++++++++++++++++--
>  1 file changed, 77 insertions(+), 6 deletions(-)
>=20
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/=
raw/brcmnand/brcmnand.c
> index ef7d340475be..e8ffc283b365 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -1038,6 +1038,22 @@ static inline int brcmnand_sector_1k_shift(struct =
brcmnand_controller *ctrl)
>  		return -1;
>  }
> =20
> +static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
> +{
> +	struct brcmnand_controller *ctrl =3D host->ctrl;
> +	int sector_size_bit =3D brcmnand_sector_1k_shift(ctrl);
> +	u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs,
> +						  BRCMNAND_CS_ACC_CONTROL);
> +	u32 acc_control;
> +
> +	if (sector_size_bit < 0)
> +		return 0;
> +
> +	acc_control =3D nand_readreg(ctrl, acc_control_offs);
> +
> +	return (acc_control & BIT(sector_size_bit)) >> sector_size_bit;

FIELD_PREP, FIELD_GET, *please*.

> +}
> +
>  static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int =
val)
>  {
>  	struct brcmnand_controller *ctrl =3D host->ctrl;
> @@ -1055,6 +1071,43 @@ static void brcmnand_set_sector_size_1k(struct brc=
mnand_host *host, int val)
>  	nand_writereg(ctrl, acc_control_offs, tmp);
>  }
> =20
> +static int brcmnand_get_spare_size(struct brcmnand_host *host)
> +{
> +	struct brcmnand_controller *ctrl =3D host->ctrl;
> +	u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs,
> +						  BRCMNAND_CS_ACC_CONTROL);
> +	u32 acc =3D nand_readreg(ctrl, acc_control_offs);
> +
> +	return (acc & brcmnand_spare_area_mask(ctrl));
> +}
> +
> +static void brcmnand_get_ecc_settings(struct brcmnand_host *host, struct=
 nand_chip *chip)
> +{
> +	struct brcmnand_controller *ctrl =3D host->ctrl;
> +	u16 acc_control_offs =3D brcmnand_cs_offset(ctrl, host->cs,
> +						  BRCMNAND_CS_ACC_CONTROL);
> +	int sector_size_1k =3D brcmnand_get_sector_size_1k(host);
> +	int spare_area_size, ecc_level;
> +	u32 acc;
> +
> +	spare_area_size =3D brcmnand_get_spare_size(host);
> +	acc =3D nand_readreg(ctrl, acc_control_offs);
> +	ecc_level =3D (acc & brcmnand_ecc_level_mask(ctrl)) >> ctrl->ecc_level_=
shift;

ditto

> +	if (sector_size_1k)
> +		chip->ecc.strength =3D ecc_level * 2;
> +	else if (spare_area_size =3D=3D 16 && ecc_level =3D=3D 15)
> +		chip->ecc.strength =3D 1; /* hamming */
> +	else
> +		chip->ecc.strength =3D ecc_level;
> +
> +	if (chip->ecc.size =3D=3D 0) {
> +		if (sector_size_1k < 0)

Should be <=3D 0 I guess

> +			chip->ecc.size =3D 512;
> +		else
> +			chip->ecc.size =3D 512 << sector_size_1k;

What is this? Are you expecting sector_size_1k to be 0 or 1
and thus multiply 512 by two?

Please just use:
			chip->ecc.size =3D SZ_1K;
		=09
> +	}
> +}
> +
>  /***********************************************************************
>   * CS_NAND_SELECT
>   ***********************************************************************/
> @@ -2625,19 +2678,37 @@ static int brcmnand_setup_dev(struct brcmnand_hos=
t *host)
>  		nanddev_get_memorg(&chip->base);
>  	struct brcmnand_controller *ctrl =3D host->ctrl;
>  	struct brcmnand_cfg *cfg =3D &host->hwcfg;
> -	char msg[128];
> +	struct device_node *np =3D nand_get_flash_node(chip);
>  	u32 offs, tmp, oob_sector;
> +	bool use_strap =3D false;
> +	char msg[128];
>  	int ret;
> =20
>  	memset(cfg, 0, sizeof(*cfg));
> +	use_strap =3D of_property_read_bool(np, "brcm,nand-ecc-use-strap");
> =20
> -	ret =3D of_property_read_u32(nand_get_flash_node(chip),
> -				   "brcm,nand-oob-sector-size",
> +	/*
> +	 * Either nand-ecc-xxx or brcm,nand-ecc-use-strap can be set. Error out
> +	 * if both exist.
> +	 */

Thanks for the comment but I think the error string is clear enough.

> +	if (chip->ecc.strength && use_strap) {
> +		dev_err(ctrl->dev,
> +			"nand ecc and strap ecc settings can't be set at the same time\n");

Can we change to
"ECC strap and DT ECC configuration properties are mutually exclusive"

> +		return -EINVAL;
> +	}
> +
> +	if (use_strap)
> +		brcmnand_get_ecc_settings(host, chip);
> +
> +	ret =3D of_property_read_u32(np, "brcm,nand-oob-sector-size",
>  				   &oob_sector);
>  	if (ret) {
> -		/* Use detected size */
> -		cfg->spare_area_size =3D mtd->oobsize /
> -					(mtd->writesize >> FC_SHIFT);
> +		if (use_strap)
> +			cfg->spare_area_size =3D brcmnand_get_spare_size(host);
> +		else
> +			/* Use detected size */
> +			cfg->spare_area_size =3D mtd->oobsize /
> +						(mtd->writesize >> FC_SHIFT);
>  	} else {
>  		cfg->spare_area_size =3D oob_sector;
>  	}

The rest of the series looks good to me.

Thanks,
Miqu=C3=A8l