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From: Zong Li <zong.li@sifive.com>
Date: Fri, 23 Feb 2024 22:04:13 +0800
Message-ID: <CANXhq0qsZS7sB-npPKdnFaWi2+yUc_dROCsVXZDHo07-a34wcw@mail.gmail.com>
Subject: Re: [PATCH 00/13] Linux RISC-V IOMMU Support
To: Tomasz Jeznach <tjeznach@rivosinc.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, 
	Robin Murphy <robin.murphy@arm.com>, Will Deacon <will@kernel.org>, Joerg Roedel <joro@8bytes.org>, 
	Anup Patel <apatel@ventanamicro.com>, Albert Ou <aou@eecs.berkeley.edu>, 
	Greentime Hu <greentime.hu@sifive.com>, linux@rivosinc.com, 
	"linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, Sebastien Boeuf <seb@rivosinc.com>, iommu@lists.linux.dev, 
	Nick Kossifidis <mick@ics.forth.gr>, linux-riscv <linux-riscv@lists.infradead.org>
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>
> The RISC-V IOMMU specification is now ratified as-per the RISC-V internat=
ional
> process [1]. The latest frozen specifcation can be found at:
> https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv=
-iommu.pdf
>
> At a high-level, the RISC-V IOMMU specification defines:
> 1) Memory-mapped programming interface
>    - Mandatory and optional registers layout and description.
>    - Software guidelines for device initialization and capabilities disco=
very.
> 2) In-memory queue interface
>    - A command-queue used by software to queue commands to the IOMMU.
>    - A fault/event queue used to bring faults and events to software=E2=
=80=99s attention.
>    - A page-request queue used to report =E2=80=9CPage Request=E2=80=9D m=
essages received from
>      PCIe devices.
>    - Message-signalled and wire-signaled interrupt mechanism.
> 3) In-memory data structures
>    - Device-context: used to associate a device with an address space and=
 to hold
>      other per-device parameters used by the IOMMU to perform address tra=
nslations.
>    - Process-contexts: used to associate a different virtual address spac=
e based on
>      device provided process identification number.
>    - MSI page table configuration used to direct an MSI to a guest interr=
upt file
>      in an IMSIC. The MSI page table formats are defined by the Advanced =
Interrupt
>      Architecture specification [2].
>
> This series introduces complete single-level translation support, includi=
ng shared
> virtual address (SVA), ATS/PRI interfaces in the kernel driver. Patches a=
dding MSI
> identity remapping and G-Stage translation (GPA to SPA) are added only to=
 excercise
> hardware interfaces, to be complemented with AIA/KVM bindings in follow-u=
p series.
>
> This series is a logical regrouping of series of incremental patches base=
d on
> RISC-V International IOMMU Task Group discussions and specification devel=
opment
> process. Original series can be found at the maintainer's repository bran=
ch [3].
>
> These patches can also be found in the riscv_iommu_v1 branch at:
> https://github.com/tjeznach/linux/tree/riscv_iommu_v1
>
> To test this series, use QEMU/OpenSBI with RISC-V IOMMU implementation av=
ailable in
> the riscv_iommu_v1 branch at:
> https://github.com/tjeznach/qemu/tree/riscv_iommu_v1
>
> References:
> [1] - https://wiki.riscv.org/display/HOME/Specification+Status
> [2] - https://github.com/riscv/riscv-aia/releases/download/1.0/riscv-inte=
rrupts-1.0.pdf
> [3] - https://github.com/tjeznach/qemu/tree/tjeznach/riscv-iommu-20230719
>
>
> Anup Patel (1):
>   dt-bindings: Add RISC-V IOMMU bindings
>
> Tomasz Jeznach (10):
>   RISC-V: drivers/iommu: Add RISC-V IOMMU - Ziommu support.
>   RISC-V: arch/riscv/config: enable RISC-V IOMMU support
>   MAINTAINERS: Add myself for RISC-V IOMMU driver
>   RISC-V: drivers/iommu/riscv: Add sysfs interface
>   RISC-V: drivers/iommu/riscv: Add command, fault, page-req queues
>   RISC-V: drivers/iommu/riscv: Add device context support
>   RISC-V: drivers/iommu/riscv: Add page table support
>   RISC-V: drivers/iommu/riscv: Add SVA with PASID/ATS/PRI support.
>   RISC-V: drivers/iommu/riscv: Add MSI identity remapping
>   RISC-V: drivers/iommu/riscv: Add G-Stage translation support
>
>  .../bindings/iommu/riscv,iommu.yaml           |  146 ++
>  MAINTAINERS                                   |    7 +
>  arch/riscv/configs/defconfig                  |    1 +
>  drivers/iommu/Kconfig                         |    1 +
>  drivers/iommu/Makefile                        |    2 +-
>  drivers/iommu/io-pgtable.c                    |    3 +
>  drivers/iommu/riscv/Kconfig                   |   22 +
>  drivers/iommu/riscv/Makefile                  |    1 +
>  drivers/iommu/riscv/io_pgtable.c              |  266 ++
>  drivers/iommu/riscv/iommu-bits.h              |  704 ++++++
>  drivers/iommu/riscv/iommu-pci.c               |  206 ++
>  drivers/iommu/riscv/iommu-platform.c          |  160 ++
>  drivers/iommu/riscv/iommu-sysfs.c             |  183 ++
>  drivers/iommu/riscv/iommu.c                   | 2130 +++++++++++++++++
>  drivers/iommu/riscv/iommu.h                   |  165 ++
>  include/linux/io-pgtable.h                    |    2 +
>  16 files changed, 3998 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/iommu/riscv,iommu.y=
aml
>  create mode 100644 drivers/iommu/riscv/Kconfig
>  create mode 100644 drivers/iommu/riscv/Makefile
>  create mode 100644 drivers/iommu/riscv/io_pgtable.c
>  create mode 100644 drivers/iommu/riscv/iommu-bits.h
>  create mode 100644 drivers/iommu/riscv/iommu-pci.c
>  create mode 100644 drivers/iommu/riscv/iommu-platform.c
>  create mode 100644 drivers/iommu/riscv/iommu-sysfs.c
>  create mode 100644 drivers/iommu/riscv/iommu.c
>  create mode 100644 drivers/iommu/riscv/iommu.h
>
> --
> 2.34.1
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Hi Tomasz,
Could I know if you have a plan for the next version and if you have
any estimates for when the v2 patch will be ready? We have some
patches based on top of your old implementation, and it would be great
if we can rebase them onto your next version. Thanks.